[PATCH 0/6] imx: add i.MX8MP hdmi blk ctrl hdcp/hrv and vpu blk ctrl

[PATCH 0/6] imx: add i.MX8MP hdmi blk ctrl hdcp/hrv and vpu blk ctrl

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

This patchset is to add more blk ctrl support for i.MX8MP
 - Add HDMI HDCP/HRV BLK CTRL support
 - Add VPU BLK CTRL support
 - Add PGC VPU node which supplies power domain for VPU BLK
This patchset is based on:
https://lore.kernel.org/all/20220708085632.1918323-1-peng.fan@oss.nxp.com/

repo: https://github.com/MrVan/linux/tree/imx8mp-blk-ctrl

Peng Fan (6):
  dt-bindings: power: imx8mp-power: add HDMI HDCP/HRV
  dt-bindings: soc: imx: add i.MX8MP vpu blk ctrl
  soc: imx: add i.MX8MP HDMI blk ctrl HDCP/HRV
  soc: imx: imx8m-blk-ctrl: add i.MX8MP VPU blk ctrl
  arm64: dts: imx8mp: add vpu pgc nodes
  arm64: dts: imx8mp: add VPU blk ctrl node

 .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml      | 17 +++++--
 arch/arm64/boot/dts/freescale/imx8mp.dtsi     | 45 ++++++++++++++++++
 drivers/soc/imx/imx8m-blk-ctrl.c              | 47 +++++++++++++++++++
 drivers/soc/imx/imx8mp-blk-ctrl.c             | 30 ++++++++++++
 include/dt-bindings/power/imx8mp-power.h      |  6 +++
 5 files changed, 142 insertions(+), 3 deletions(-)

-- 
2.25.1

[PATCH 1/6] dt-bindings: power: imx8mp-power: add HDMI HDCP/HRV

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Add i.MX8MP HDMI HDCP and HRV entries.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 include/dt-bindings/power/imx8mp-power.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h
index 7789bcca3223..14b9c5ac9c82 100644
--- a/include/dt-bindings/power/imx8mp-power.h
+++ b/include/dt-bindings/power/imx8mp-power.h
@@ -49,5 +49,7 @@
 #define IMX8MP_HDMIBLK_PD_TRNG				4
 #define IMX8MP_HDMIBLK_PD_HDMI_TX			5
 #define IMX8MP_HDMIBLK_PD_HDMI_TX_PHY			6
+#define IMX8MP_HDMIBLK_PD_HDCP				7
+#define IMX8MP_HDMIBLK_PD_HRV				8
 
 #endif
-- 
2.25.1

Re: [PATCH 1/6] dt-bindings: power: imx8mp-power: add HDMI HDCP/HRV

[Krzysztof Kozlowski]

On 12/07/2022 10:21, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> Add i.MX8MP HDMI HDCP and HRV entries.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

[PATCH 2/6] dt-bindings: soc: imx: add i.MX8MP vpu blk ctrl

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

i.MX8MP VPU blk ctrl module has similar design as i.MX8MM, so reuse
the i.MX8MM VPU blk ctrl yaml file.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml        | 17 ++++++++++++++---
 include/dt-bindings/power/imx8mp-power.h        |  4 ++++
 2 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
index 26487daa64d9..edbd267cdd67 100644
--- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
@@ -4,20 +4,22 @@
 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: NXP i.MX8MM VPU blk-ctrl
+title: NXP i.MX8MM/P VPU blk-ctrl
 
 maintainers:
   - Lucas Stach <l.stach@pengutronix.de>
 
 description:
-  The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to
+  The i.MX8MM/P VPU blk-ctrl is a top-level peripheral providing access to
   the NoC and ensuring proper power sequencing of the VPU peripherals
   located in the VPU domain of the SoC.
 
 properties:
   compatible:
     items:
-      - const: fsl,imx8mm-vpu-blk-ctrl
+      - enum:
+          - fsl,imx8mm-vpu-blk-ctrl
+          - fsl,imx8mp-vpu-blk-ctrl
       - const: syscon
 
   reg:
@@ -47,6 +49,15 @@ properties:
       - const: g2
       - const: h1
 
+  interconnects:
+    maxItems: 3
+
+  interconnect-names:
+    items:
+      - const: g1
+      - const: g2
+      - const: h1
+
 required:
   - compatible
   - reg
diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h
index 14b9c5ac9c82..11d43fc7a18e 100644
--- a/include/dt-bindings/power/imx8mp-power.h
+++ b/include/dt-bindings/power/imx8mp-power.h
@@ -52,4 +52,8 @@
 #define IMX8MP_HDMIBLK_PD_HDCP				7
 #define IMX8MP_HDMIBLK_PD_HRV				8
 
+#define IMX8MP_VPUBLK_PD_G1				0
+#define IMX8MP_VPUBLK_PD_G2				1
+#define IMX8MP_VPUBLK_PD_H1				2
+
 #endif
-- 
2.25.1

Re: [PATCH 2/6] dt-bindings: soc: imx: add i.MX8MP vpu blk ctrl

[Krzysztof Kozlowski]

On 12/07/2022 10:21, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> i.MX8MP VPU blk ctrl module has similar design as i.MX8MM, so reuse
> the i.MX8MM VPU blk ctrl yaml file.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml        | 17 ++++++++++++++---
>  include/dt-bindings/power/imx8mp-power.h        |  4 ++++
>  2 files changed, 18 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
> index 26487daa64d9..edbd267cdd67 100644
> --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
> +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
> @@ -4,20 +4,22 @@
>  $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml#
>  $schema: http://devicetree.org/meta-schemas/core.yaml#
>  
> -title: NXP i.MX8MM VPU blk-ctrl
> +title: NXP i.MX8MM/P VPU blk-ctrl
>  
>  maintainers:
>    - Lucas Stach <l.stach@pengutronix.de>
>  
>  description:
> -  The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to
> +  The i.MX8MM/P VPU blk-ctrl is a top-level peripheral providing access to
>    the NoC and ensuring proper power sequencing of the VPU peripherals
>    located in the VPU domain of the SoC.
>  
>  properties:
>    compatible:
>      items:
> -      - const: fsl,imx8mm-vpu-blk-ctrl
> +      - enum:
> +          - fsl,imx8mm-vpu-blk-ctrl
> +          - fsl,imx8mp-vpu-blk-ctrl
>        - const: syscon
>  
>    reg:
> @@ -47,6 +49,15 @@ properties:
>        - const: g2
>        - const: h1
>  
> +  interconnects:
> +    maxItems: 3

You should describe the items, because g1/g2/h1 are quite cryptic.


Best regards,
Krzysztof

Re: [PATCH 2/6] dt-bindings: soc: imx: add i.MX8MP vpu blk ctrl

[Adam Ford]

On Tue, Jul 12, 2022 at 3:20 AM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>
> From: Peng Fan <peng.fan@nxp.com>
>
> i.MX8MP VPU blk ctrl module has similar design as i.MX8MM, so reuse
> the i.MX8MM VPU blk ctrl yaml file.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml        | 17 ++++++++++++++---
>  include/dt-bindings/power/imx8mp-power.h        |  4 ++++
>  2 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
> index 26487daa64d9..edbd267cdd67 100644
> --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
> +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
> @@ -4,20 +4,22 @@
>  $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml#
>  $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: NXP i.MX8MM VPU blk-ctrl
> +title: NXP i.MX8MM/P VPU blk-ctrl
>
>  maintainers:
>    - Lucas Stach <l.stach@pengutronix.de>
>
>  description:
> -  The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to
> +  The i.MX8MM/P VPU blk-ctrl is a top-level peripheral providing access to
>    the NoC and ensuring proper power sequencing of the VPU peripherals
>    located in the VPU domain of the SoC.
>
>  properties:
>    compatible:
>      items:
> -      - const: fsl,imx8mm-vpu-blk-ctrl
> +      - enum:
> +          - fsl,imx8mm-vpu-blk-ctrl
> +          - fsl,imx8mp-vpu-blk-ctrl
>        - const: syscon
>
>    reg:
> @@ -47,6 +49,15 @@ properties:
>        - const: g2
>        - const: h1
>
> +  interconnects:
> +    maxItems: 3
> +
> +  interconnect-names:
> +    items:
> +      - const: g1
> +      - const: g2
> +      - const: h1
> +
>  required:
>    - compatible
>    - reg
> diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h
> index 14b9c5ac9c82..11d43fc7a18e 100644
> --- a/include/dt-bindings/power/imx8mp-power.h
> +++ b/include/dt-bindings/power/imx8mp-power.h
> @@ -52,4 +52,8 @@
>  #define IMX8MP_HDMIBLK_PD_HDCP                         7
>  #define IMX8MP_HDMIBLK_PD_HRV                          8
>
> +#define IMX8MP_VPUBLK_PD_G1                            0
> +#define IMX8MP_VPUBLK_PD_G2                            1
> +#define IMX8MP_VPUBLK_PD_H1                            2

Is H1 even correct for 8MP? The TRM calls the encoder a VC800E.  Since
the Encoder on the 8MM is a Hantro H1, this might add confusion if
people start thinking they are the same.
> +
>  #endif
> --
> 2.25.1
>

RE: [PATCH 2/6] dt-bindings: soc: imx: add i.MX8MP vpu blk ctrl

[Peng Fan]

> Subject: Re: [PATCH 2/6] dt-bindings: soc: imx: add i.MX8MP vpu blk ctrl
> 
> On Tue, Jul 12, 2022 at 3:20 AM Peng Fan (OSS) <peng.fan@oss.nxp.com>
> wrote:
> >
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > i.MX8MP VPU blk ctrl module has similar design as i.MX8MM, so reuse
> > the i.MX8MM VPU blk ctrl yaml file.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml        | 17 ++++++++++++++---
> >  include/dt-bindings/power/imx8mp-power.h        |  4 ++++
> >  2 files changed, 18 insertions(+), 3 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-
> ctrl.ya
> > ml
> > b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-
> ctrl.ya
> > ml index 26487daa64d9..edbd267cdd67 100644
> > ---
> > a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-
> ctrl.ya
> > ml
> > +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-
> ctr
> > +++ l.yaml
> > @@ -4,20 +4,22 @@
> >  $id:
> >
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevic
> > etree.org%2Fschemas%2Fsoc%2Fimx%2Ffsl%2Cimx8mm-vpu-blk-
> ctrl.yaml%23&am
> >
> p;data=05%7C01%7Cpeng.fan%40nxp.com%7Cc99b7cd9f40b4e5ecf8a08da6
> 3ffb350
> > %7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63793224713390
> 0894%7CUnk
> >
> nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6I
> k1haWw
> >
> iLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=uiVz0so%2BdmCPhOu
> I3Lf1cJBfs0
> > kmBYa5J4Ak8uWxk%2Fk%3D&amp;reserved=0
> >  $schema:
> >
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevic
> > etree.org%2Fmeta-
> schemas%2Fcore.yaml%23&amp;data=05%7C01%7Cpeng.fan%40
> >
> nxp.com%7Cc99b7cd9f40b4e5ecf8a08da63ffb350%7C686ea1d3bc2b4c6fa92
> cd99c5
> >
> c301635%7C0%7C0%7C637932247133900894%7CUnknown%7CTWFpbGZsb
> 3d8eyJWIjoiM
> >
> C4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000
> %7C%7C
> > %7C&amp;sdata=4y71i22hEKKd8D16qHOMsK%2F%2FDfsV1IL17iioMm9lw
> %2Fk%3D&amp
> > ;reserved=0
> >
> > -title: NXP i.MX8MM VPU blk-ctrl
> > +title: NXP i.MX8MM/P VPU blk-ctrl
> >
> >  maintainers:
> >    - Lucas Stach <l.stach@pengutronix.de>
> >
> >  description:
> > -  The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access
> > to
> > +  The i.MX8MM/P VPU blk-ctrl is a top-level peripheral providing
> > + access to
> >    the NoC and ensuring proper power sequencing of the VPU peripherals
> >    located in the VPU domain of the SoC.
> >
> >  properties:
> >    compatible:
> >      items:
> > -      - const: fsl,imx8mm-vpu-blk-ctrl
> > +      - enum:
> > +          - fsl,imx8mm-vpu-blk-ctrl
> > +          - fsl,imx8mp-vpu-blk-ctrl
> >        - const: syscon
> >
> >    reg:
> > @@ -47,6 +49,15 @@ properties:
> >        - const: g2
> >        - const: h1
> >
> > +  interconnects:
> > +    maxItems: 3
> > +
> > +  interconnect-names:
> > +    items:
> > +      - const: g1
> > +      - const: g2
> > +      - const: h1
> > +
> >  required:
> >    - compatible
> >    - reg
> > diff --git a/include/dt-bindings/power/imx8mp-power.h
> > b/include/dt-bindings/power/imx8mp-power.h
> > index 14b9c5ac9c82..11d43fc7a18e 100644
> > --- a/include/dt-bindings/power/imx8mp-power.h
> > +++ b/include/dt-bindings/power/imx8mp-power.h
> > @@ -52,4 +52,8 @@
> >  #define IMX8MP_HDMIBLK_PD_HDCP                         7
> >  #define IMX8MP_HDMIBLK_PD_HRV                          8
> >
> > +#define IMX8MP_VPUBLK_PD_G1                            0
> > +#define IMX8MP_VPUBLK_PD_G2                            1
> > +#define IMX8MP_VPUBLK_PD_H1                            2
> 
> Is H1 even correct for 8MP? The TRM calls the encoder a VC800E.  Since the
> Encoder on the 8MM is a Hantro H1, this might add confusion if people start
> thinking they are the same.

VC8000E should be used, I'll update.

Thanks,
Peng.

> > +
> >  #endif
> > --
> > 2.25.1
> >

[PATCH 3/6] soc: imx: add i.MX8MP HDMI blk ctrl HDCP/HRV

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

i.MX8MP HDMI supports HDCP and HRV, so add them.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/soc/imx/imx8mp-blk-ctrl.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c
index 6f983adcb47c..527d45d12a54 100644
--- a/drivers/soc/imx/imx8mp-blk-ctrl.c
+++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
@@ -235,6 +235,13 @@ static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
 		regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
 		break;
+	case IMX8MP_HDMIBLK_PD_HDCP:
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));
+		break;
+	case IMX8MP_HDMIBLK_PD_HRV:
+		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));
+		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));
+		break;
 	default:
 		break;
 	}
@@ -283,6 +290,13 @@ static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
 		break;
+	case IMX8MP_HDMIBLK_PD_HDCP:
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));
+		break;
+	case IMX8MP_HDMIBLK_PD_HRV:
+		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));
+		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));
+		break;
 	default:
 		break;
 	}
@@ -365,6 +379,22 @@ static const struct imx8mp_blk_ctrl_domain_data imx8mp_hdmi_domain_data[] = {
 		.num_clks = 2,
 		.gpc_name = "hdmi-tx-phy",
 	},
+	[IMX8MP_HDMIBLK_PD_HRV] = {
+		.name = "hdmiblk-hrv",
+		.clk_names = (const char *[]){ "axi", "apb" },
+		.num_clks = 2,
+		.gpc_name = "hrv",
+		.path_names = (const char *[]){"hrv"},
+		.num_paths = 1,
+	},
+	[IMX8MP_HDMIBLK_PD_HDCP] = {
+		.name = "hdmiblk-hdcp",
+		.clk_names = (const char *[]){ "axi", "apb" },
+		.num_clks = 2,
+		.gpc_name = "hdcp",
+		.path_names = (const char *[]){"hdcp"},
+		.num_paths = 1,
+	},
 };
 
 static const struct imx8mp_blk_ctrl_data imx8mp_hdmi_blk_ctl_dev_data = {
-- 
2.25.1

[PATCH 4/6] soc: imx: imx8m-blk-ctrl: add i.MX8MP VPU blk ctrl

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

i.MX8MP has a VPU blk ctrl module that could supply clk and reset to
VPU, so add support for it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/soc/imx/imx8m-blk-ctrl.c | 47 ++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
index 9b0f81dc292b..d958d2f0cc73 100644
--- a/drivers/soc/imx/imx8m-blk-ctrl.c
+++ b/drivers/soc/imx/imx8m-blk-ctrl.c
@@ -484,6 +484,50 @@ static const struct imx8m_blk_ctrl_data imx8mm_vpu_blk_ctl_dev_data = {
 	.num_domains = ARRAY_SIZE(imx8mm_vpu_blk_ctl_domain_data),
 };
 
+#define IMX8MP_VPUBLK_G1	0
+#define IMX8MP_VPUBLK_G2	1
+#define IMX8MP_VPUBLK_VCE	2
+
+static const struct imx8m_blk_ctrl_domain_data imx8mp_vpu_blk_ctl_domain_data[] = {
+	[IMX8MP_VPUBLK_PD_G1] = {
+		.name = "vpublk-g1",
+		.clk_names = (const char *[]){ "g1", },
+		.num_clks = 1,
+		.gpc_name = "g1",
+		.rst_mask = BIT(1),
+		.clk_mask = BIT(1),
+		.path_names = (const char *[]){"g1"},
+		.num_paths = 1,
+	},
+	[IMX8MP_VPUBLK_PD_G2] = {
+		.name = "vpublk-g2",
+		.clk_names = (const char *[]){ "g2", },
+		.num_clks = 1,
+		.gpc_name = "g2",
+		.rst_mask = BIT(0),
+		.clk_mask = BIT(0),
+		.path_names = (const char *[]){"g2"},
+		.num_paths = 1,
+	},
+	[IMX8MP_VPUBLK_PD_H1] = {
+		.name = "vpublk-h1",
+		.clk_names = (const char *[]){ "h1", },
+		.num_clks = 1,
+		.gpc_name = "h1",
+		.rst_mask = BIT(2),
+		.clk_mask = BIT(2),
+		.path_names = (const char *[]){"h1"},
+		.num_paths = 1,
+	},
+};
+
+static const struct imx8m_blk_ctrl_data imx8mp_vpu_blk_ctl_dev_data = {
+	.max_reg = 0x18,
+	.power_notifier_fn = imx8mm_vpu_power_notifier,
+	.domains = imx8mp_vpu_blk_ctl_domain_data,
+	.num_domains = ARRAY_SIZE(imx8mp_vpu_blk_ctl_domain_data),
+};
+
 static int imx8mm_disp_power_notifier(struct notifier_block *nb,
 				      unsigned long action, void *data)
 {
@@ -827,6 +871,9 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
 	}, {
 		.compatible = "fsl,imx8mq-vpu-blk-ctrl",
 		.data = &imx8mq_vpu_blk_ctl_dev_data
+	}, {
+		.compatible = "fsl,imx8mp-vpu-blk-ctrl",
+		.data = &imx8mp_vpu_blk_ctl_dev_data
 	}, {
 		/* Sentinel */
 	}
-- 
2.25.1

[PATCH 5/6] arm64: dts: imx8mp: add vpu pgc nodes

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Add i.MX8MP PGC nodes for vpu, which are used to supply power for VPU.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 27 +++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 0b165f98a82c..fb52404f4cdf 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -598,6 +598,33 @@ pgc_ispdwp: power-domain@18 {
 						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
 						clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
 					};
+
+					pgc_vpumix: power-domain@19 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
+						clocks =<&clk IMX8MP_CLK_VPU_ROOT>;
+					};
+
+					pgc_vpu_g1: power-domain@20 {
+						#power-domain-cells = <0>;
+						power-domains = <&pgc_vpumix>;
+						reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;
+						clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
+					};
+
+					pgc_vpu_g2: power-domain@21 {
+						#power-domain-cells = <0>;
+						power-domains = <&pgc_vpumix>;
+						reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;
+						clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
+					};
+
+					pgc_vpu_h1: power-domain@22 {
+						#power-domain-cells = <0>;
+						power-domains = <&pgc_vpumix>;
+						reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
+						clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
+					};
 				};
 			};
 		};
-- 
2.25.1

[PATCH 6/6] arm64: dts: imx8mp: add VPU blk ctrl node

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Add i.MX8MP VPU blk ctrl node

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index fb52404f4cdf..b906aabf0685 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1185,6 +1185,24 @@ gic: interrupt-controller@38800000 {
 			interrupt-parent = <&gic>;
 		};
 
+		vpumix_blk_ctl: blk-ctl@38330000 {
+			compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
+			reg = <0x38330000 0x100>;
+			#power-domain-cells = <1>;
+			power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
+					<&pgc_vpu_g2>, <&pgc_vpu_h1>;
+			power-domain-names = "bus", "g1", "g2", "h1";
+			clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>,
+				 <&clk IMX8MP_CLK_VPU_G2_ROOT>,
+				 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
+			clock-names = "g1", "g2", "h1";
+			interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>,
+					<&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>,
+					<&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;
+			interconnect-names = "g1", "g2", "h1";
+		};
+
+
 		edacmc: memory-controller@3d400000 {
 			compatible = "snps,ddrc-3.80a";
 			reg = <0x3d400000 0x400000>;
-- 
2.25.1