* [PATCH v2 1/4] irqchip: allow pass down .pm field at IRQCHIP_PLATFORM_DRIVER_END
2022-07-15 19:22 [PATCH v2 0/4] PCI EP driver support MSI doorbell from host Frank Li
@ 2022-07-15 19:22 ` Frank Li
2022-07-15 19:22 ` [PATCH v2 2/4] irqchip: imx mu worked as msi controller Frank Li
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Frank Li @ 2022-07-15 19:22 UTC (permalink / raw)
To: maz, tglx, robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer, kw,
bhelgaas
Cc: kernel, devicetree, linux-arm-kernel, linux-pci, peng.fan,
aisheng.dong, jdmason, kernel, festevam, linux-imx, kishon,
lorenzo.pieralisi, ntb
IRQCHIP_PLATFORM_DRIVER_* compilation define platform_driver
for irqchip. But can't set .pm field of platform_driver.
Added variadic macros to set .pm field or other field if need.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
include/linux/irqchip.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/linux/irqchip.h b/include/linux/irqchip.h
index 3a091d0710ae1..d5e6024cb2a8c 100644
--- a/include/linux/irqchip.h
+++ b/include/linux/irqchip.h
@@ -44,7 +44,8 @@ static const struct of_device_id drv_name##_irqchip_match_table[] = {
#define IRQCHIP_MATCH(compat, fn) { .compatible = compat, \
.data = typecheck_irq_init_cb(fn), },
-#define IRQCHIP_PLATFORM_DRIVER_END(drv_name) \
+
+#define IRQCHIP_PLATFORM_DRIVER_END(drv_name, ...) \
{}, \
}; \
MODULE_DEVICE_TABLE(of, drv_name##_irqchip_match_table); \
@@ -56,6 +57,7 @@ static struct platform_driver drv_name##_driver = { \
.owner = THIS_MODULE, \
.of_match_table = drv_name##_irqchip_match_table, \
.suppress_bind_attrs = true, \
+ __VA_ARGS__ \
}, \
}; \
builtin_platform_driver(drv_name##_driver)
--
2.35.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 2/4] irqchip: imx mu worked as msi controller
2022-07-15 19:22 [PATCH v2 0/4] PCI EP driver support MSI doorbell from host Frank Li
2022-07-15 19:22 ` [PATCH v2 1/4] irqchip: allow pass down .pm field at IRQCHIP_PLATFORM_DRIVER_END Frank Li
@ 2022-07-15 19:22 ` Frank Li
2022-07-15 19:22 ` [PATCH v2 3/4] dt-bindings: irqchip: imx mu work " Frank Li
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Frank Li @ 2022-07-15 19:22 UTC (permalink / raw)
To: maz, tglx, robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer, kw,
bhelgaas
Cc: kernel, devicetree, linux-arm-kernel, linux-pci, peng.fan,
aisheng.dong, jdmason, kernel, festevam, linux-imx, kishon,
lorenzo.pieralisi, ntb
MU support generate irq by write data to a register.
This patch make mu worked as msi controller.
So MU can do doorbell by using standard msi api.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/irqchip/Kconfig | 7 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-imx-mu-msi.c | 462 +++++++++++++++++++++++++++++++
3 files changed, 470 insertions(+)
create mode 100644 drivers/irqchip/irq-imx-mu-msi.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 5e4e50122777d..4599471d880c0 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -470,6 +470,13 @@ config IMX_INTMUX
help
Support for the i.MX INTMUX interrupt multiplexer.
+config IMX_MU_MSI
+ bool "i.MX MU work as MSI controller"
+ default y if ARCH_MXC
+ select IRQ_DOMAIN
+ help
+ MU work as MSI controller to do general doorbell
+
config LS1X_IRQ
bool "Loongson-1 Interrupt Controller"
depends on MACH_LOONGSON32
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 5d8e21d3dc6d8..870423746c783 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o
obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o
obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o
obj-$(CONFIG_IMX_INTMUX) += irq-imx-intmux.o
+obj-$(CONFIG_IMX_MU_MSI) += irq-imx-mu-msi.o
obj-$(CONFIG_MADERA_IRQ) += irq-madera.o
obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
diff --git a/drivers/irqchip/irq-imx-mu-msi.c b/drivers/irqchip/irq-imx-mu-msi.c
new file mode 100644
index 0000000000000..8277dba857759
--- /dev/null
+++ b/drivers/irqchip/irq-imx-mu-msi.c
@@ -0,0 +1,462 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * NXP MU worked as MSI controller
+ *
+ * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
+ * Copyright 2022 NXP
+ * Frank Li <Frank.Li@nxp.com>
+ * Peng Fan <peng.fan@nxp.com>
+ *
+ * Based on drivers/mailbox/imx-mailbox.c
+ */
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/msi.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/spinlock.h>
+#include <linux/dma-iommu.h>
+#include <linux/pm_runtime.h>
+#include <linux/pm_domain.h>
+
+
+#define IMX_MU_CHANS 4
+
+enum imx_mu_xcr {
+ IMX_MU_GIER,
+ IMX_MU_GCR,
+ IMX_MU_TCR,
+ IMX_MU_RCR,
+ IMX_MU_xCR_MAX,
+};
+
+enum imx_mu_xsr {
+ IMX_MU_SR,
+ IMX_MU_GSR,
+ IMX_MU_TSR,
+ IMX_MU_RSR,
+};
+
+enum imx_mu_type {
+ IMX_MU_V1 = BIT(0),
+ IMX_MU_V2 = BIT(1),
+ IMX_MU_V2_S4 = BIT(15),
+};
+
+/* Receive Interrupt Enable */
+#define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
+#define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
+
+struct imx_mu_dcfg {
+ enum imx_mu_type type;
+ u32 xTR; /* Transmit Register0 */
+ u32 xRR; /* Receive Register0 */
+ u32 xSR[4]; /* Status Registers */
+ u32 xCR[4]; /* Control Registers */
+};
+
+struct imx_mu_msi {
+ spinlock_t lock;
+ struct platform_device *pdev;
+ struct irq_domain *parent;
+ struct irq_domain *msi_domain;
+ void __iomem *regs;
+ phys_addr_t msiir_addr;
+ const struct imx_mu_dcfg *cfg;
+ unsigned long used;
+ u32 gic_irq;
+ struct clk *clk;
+ struct device *pd_a;
+ struct device *pd_b;
+ struct device_link *pd_link_a;
+ struct device_link *pd_link_b;
+};
+
+static void imx_mu_write(struct imx_mu_msi *msi_data, u32 val, u32 offs)
+{
+ iowrite32(val, msi_data->regs + offs);
+}
+
+static u32 imx_mu_read(struct imx_mu_msi *msi_data, u32 offs)
+{
+ return ioread32(msi_data->regs + offs);
+}
+
+static u32 imx_mu_xcr_rmw(struct imx_mu_msi *msi_data, enum imx_mu_xcr type, u32 set, u32 clr)
+{
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&msi_data->lock, flags);
+ val = imx_mu_read(msi_data, msi_data->cfg->xCR[type]);
+ val &= ~clr;
+ val |= set;
+ imx_mu_write(msi_data, val, msi_data->cfg->xCR[type]);
+ spin_unlock_irqrestore(&msi_data->lock, flags);
+
+ return val;
+}
+
+static void imx_mu_msi_mask_irq(struct irq_data *data)
+{
+ struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data->parent_data);
+
+ imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(msi_data->cfg->type, data->hwirq));
+}
+
+static void imx_mu_msi_unmask_irq(struct irq_data *data)
+{
+ struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data->parent_data);
+
+ imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, IMX_MU_xCR_RIEn(msi_data->cfg->type, data->hwirq), 0);
+}
+
+static struct irq_chip imx_mu_msi_irq_chip = {
+ .name = "MU-MSI",
+ .irq_mask = imx_mu_msi_mask_irq,
+ .irq_unmask = imx_mu_msi_unmask_irq,
+};
+
+static struct msi_domain_ops its_pmsi_ops = {
+};
+
+static struct msi_domain_info imx_mu_msi_domain_info = {
+ .flags = (MSI_FLAG_USE_DEF_DOM_OPS |
+ MSI_FLAG_USE_DEF_CHIP_OPS |
+ MSI_FLAG_PCI_MSIX),
+ .ops = &its_pmsi_ops,
+ .chip = &imx_mu_msi_irq_chip,
+};
+
+static void imx_mu_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
+{
+ struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data);
+
+ msg->address_hi = upper_32_bits(msi_data->msiir_addr);
+ msg->address_lo = lower_32_bits(msi_data->msiir_addr + 4 * data->hwirq);
+ msg->data = data->hwirq;
+
+ iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg);
+}
+
+static int imx_mu_msi_set_affinity(struct irq_data *irq_data,
+ const struct cpumask *mask, bool force)
+
+{
+ return IRQ_SET_MASK_OK;
+}
+
+static struct irq_chip imx_mu_msi_parent_chip = {
+ .name = "MU",
+ .irq_compose_msi_msg = imx_mu_msi_compose_msg,
+ .irq_set_affinity = imx_mu_msi_set_affinity,
+};
+
+static int imx_mu_msi_domain_irq_alloc(struct irq_domain *domain,
+ unsigned int virq,
+ unsigned int nr_irqs,
+ void *args)
+{
+ struct imx_mu_msi *msi_data = domain->host_data;
+ msi_alloc_info_t *info = args;
+ int pos, err = 0;
+
+ WARN_ON(nr_irqs != 1);
+
+ spin_lock(&msi_data->lock);
+ pos = find_first_zero_bit(&msi_data->used, IMX_MU_CHANS);
+ if (pos < IMX_MU_CHANS)
+ __set_bit(pos, &msi_data->used);
+ else
+ err = -ENOSPC;
+ spin_unlock(&msi_data->lock);
+
+ if (err)
+ return err;
+
+ err = iommu_dma_prepare_msi(info->desc, msi_data->msiir_addr + pos * 4);
+ if (err)
+ return err;
+
+ irq_domain_set_info(domain, virq, pos,
+ &imx_mu_msi_parent_chip, msi_data,
+ handle_simple_irq, NULL, NULL);
+ return 0;
+}
+
+static void imx_mu_msi_domain_irq_free(struct irq_domain *domain,
+ unsigned int virq, unsigned int nr_irqs)
+{
+ struct irq_data *d = irq_domain_get_irq_data(domain, virq);
+ struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(d);
+
+ spin_lock(&msi_data->lock);
+ __clear_bit(d->hwirq, &msi_data->used);
+ spin_unlock(&msi_data->lock);
+}
+
+static const struct irq_domain_ops imx_mu_msi_domain_ops = {
+ .alloc = imx_mu_msi_domain_irq_alloc,
+ .free = imx_mu_msi_domain_irq_free,
+};
+
+static void imx_mu_msi_irq_handler(struct irq_desc *desc)
+{
+ struct imx_mu_msi *msi_data = irq_desc_get_handler_data(desc);
+ u32 status;
+ int i;
+
+ status = imx_mu_read(msi_data, msi_data->cfg->xSR[IMX_MU_RSR]);
+
+ chained_irq_enter(irq_desc_get_chip(desc), desc);
+ for (i = 0; i < IMX_MU_CHANS; i++) {
+ if (status & IMX_MU_xSR_RFn(msi_data->cfg->type, i)) {
+ imx_mu_read(msi_data, msi_data->cfg->xRR + i * 4);
+ generic_handle_domain_irq(msi_data->parent, i);
+ }
+ }
+ chained_irq_exit(irq_desc_get_chip(desc), desc);
+}
+
+static int imx_mu_msi_domains_init(struct imx_mu_msi *msi_data)
+{
+ /* Initialize MSI domain parent */
+ msi_data->parent = irq_domain_add_linear(dev_of_node(&msi_data->pdev->dev),
+ IMX_MU_CHANS,
+ &imx_mu_msi_domain_ops,
+ msi_data);
+ if (!msi_data->parent) {
+ dev_err(&msi_data->pdev->dev, "failed to create IRQ domain\n");
+ return -ENOMEM;
+ }
+
+ msi_data->msi_domain = platform_msi_create_irq_domain(
+ of_node_to_fwnode(msi_data->pdev->dev.of_node),
+ &imx_mu_msi_domain_info,
+ msi_data->parent);
+
+ if (!msi_data->msi_domain) {
+ dev_err(&msi_data->pdev->dev, "failed to create MSI domain\n");
+ irq_domain_remove(msi_data->parent);
+ return -ENOMEM;
+ }
+
+ irq_domain_set_pm_device(msi_data->parent, &msi_data->pdev->dev);
+
+ return 0;
+}
+
+/* Register offset of different version MU IP */
+static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
+ .xTR = 0x0,
+ .xRR = 0x10,
+ .xSR = {0x20, 0x20, 0x20, 0x20},
+ .xCR = {0x24, 0x24, 0x24, 0x24},
+};
+
+static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
+ .xTR = 0x20,
+ .xRR = 0x40,
+ .xSR = {0x60, 0x60, 0x60, 0x60},
+ .xCR = {0x64, 0x64, 0x64, 0x64},
+};
+
+static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
+ .type = IMX_MU_V2,
+ .xTR = 0x200,
+ .xRR = 0x280,
+ .xSR = {0xC, 0x118, 0x124, 0x12C},
+ .xCR = {0x110, 0x114, 0x120, 0x128},
+};
+
+static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = {
+
+ .type = IMX_MU_V2 | IMX_MU_V2_S4,
+ .xTR = 0x200,
+ .xRR = 0x280,
+ .xSR = {0xC, 0x118, 0x124, 0x12C},
+ .xCR = {0x110, 0x114, 0x120, 0x128},
+};
+
+static int __init imx_mu_of_init(struct device_node *dn,
+ struct device_node *parent,
+ const struct imx_mu_dcfg *cfg)
+{
+ struct platform_device *pdev = of_find_device_by_node(dn);
+ struct imx_mu_msi *msi_data, *priv;
+ struct resource *res;
+ struct device *dev;
+ int ret;
+
+ if (!pdev)
+ return -ENODEV;
+
+ dev = &pdev->dev;
+
+ priv = msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL);
+ if (!msi_data)
+ return -ENOMEM;
+
+ msi_data->cfg = cfg;
+
+ msi_data->regs = devm_platform_ioremap_resource_byname(pdev, "a");
+ if (IS_ERR(msi_data->regs)) {
+ dev_err(&pdev->dev, "failed to initialize 'regs'\n");
+ return PTR_ERR(msi_data->regs);
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "b");
+ if (!res)
+ return -EIO;
+
+ msi_data->msiir_addr = res->start + msi_data->cfg->xTR;
+
+ msi_data->pdev = pdev;
+
+ msi_data->gic_irq = platform_get_irq(msi_data->pdev, 0);
+ if (msi_data->gic_irq <= 0)
+ return -ENODEV;
+
+ platform_set_drvdata(pdev, msi_data);
+
+ msi_data->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(msi_data->clk)) {
+ if (PTR_ERR(msi_data->clk) != -ENOENT)
+ return PTR_ERR(msi_data->clk);
+
+ msi_data->clk = NULL;
+ }
+
+ ret = clk_prepare_enable(msi_data->clk);
+ if (ret) {
+ dev_err(dev, "Failed to enable clock\n");
+ return ret;
+ }
+
+ priv->pd_a = dev_pm_domain_attach_by_name(dev, "a");
+ if (IS_ERR(priv->pd_a))
+ return PTR_ERR(priv->pd_a);
+
+ priv->pd_link_a = device_link_add(dev, priv->pd_a,
+ DL_FLAG_STATELESS |
+ DL_FLAG_PM_RUNTIME |
+ DL_FLAG_RPM_ACTIVE);
+
+ if (!priv->pd_link_a) {
+ dev_err(dev, "Failed to add device_link to mu a.\n");
+ return -EINVAL;
+ }
+
+ priv->pd_b = dev_pm_domain_attach_by_name(dev, "b");
+ if (IS_ERR(priv->pd_b))
+ return PTR_ERR(priv->pd_b);
+
+ priv->pd_link_b = device_link_add(dev, priv->pd_b,
+ DL_FLAG_STATELESS |
+ DL_FLAG_PM_RUNTIME |
+ DL_FLAG_RPM_ACTIVE);
+
+ if (!priv->pd_link_b) {
+ dev_err(dev, "Failed to add device_link to mu a.\n");
+ return -EINVAL;
+ }
+
+ ret = imx_mu_msi_domains_init(msi_data);
+ if (ret)
+ return ret;
+
+ irq_set_chained_handler_and_data(msi_data->gic_irq,
+ imx_mu_msi_irq_handler,
+ msi_data);
+
+ pm_runtime_enable(dev);
+
+ ret = pm_runtime_get_sync(dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(dev);
+ goto disable_runtime_pm;
+ }
+
+ ret = pm_runtime_put_sync(dev);
+ if (ret < 0)
+ goto disable_runtime_pm;
+
+ clk_disable_unprepare(msi_data->clk);
+
+ return 0;
+
+disable_runtime_pm:
+ pm_runtime_disable(dev);
+ clk_disable_unprepare(msi_data->clk);
+
+ return ret;
+}
+
+static int __maybe_unused imx_mu_runtime_suspend(struct device *dev)
+{
+ struct imx_mu_msi *priv = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(priv->clk);
+
+ return 0;
+}
+
+static int __maybe_unused imx_mu_runtime_resume(struct device *dev)
+{
+ struct imx_mu_msi *priv = dev_get_drvdata(dev);
+ int ret;
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret)
+ dev_err(dev, "failed to enable clock\n");
+
+ return ret;
+}
+
+static const struct dev_pm_ops imx_mu_pm_ops = {
+ SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend,
+ imx_mu_runtime_resume, NULL)
+};
+
+static int __init imx_mu_imx7ulp_of_init(struct device_node *dn,
+ struct device_node *parent)
+{
+ return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx7ulp);
+}
+
+static int __init imx_mu_imx6sx_of_init(struct device_node *dn,
+ struct device_node *parent)
+{
+ return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx6sx);
+}
+
+static int __init imx_mu_imx8ulp_of_init(struct device_node *dn,
+ struct device_node *parent)
+{
+ return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx8ulp);
+}
+
+static int __init imx_mu_imx8ulp_s4_of_init(struct device_node *dn,
+ struct device_node *parent)
+{
+ return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx8ulp_s4);
+}
+
+IRQCHIP_PLATFORM_DRIVER_BEGIN(imx_mu_msi)
+IRQCHIP_MATCH("fsl,imx7ulp-mu-msi", imx_mu_imx7ulp_of_init)
+IRQCHIP_MATCH("fsl,imx6sx-mu-msi", imx_mu_imx6sx_of_init)
+IRQCHIP_MATCH("fsl,imx8ulp-mu-msi", imx_mu_imx8ulp_of_init)
+IRQCHIP_MATCH("fsl,imx8ulp-mu-msi-s4", imx_mu_imx8ulp_s4_of_init)
+IRQCHIP_PLATFORM_DRIVER_END(imx_mu_msi, .pm = &imx_mu_pm_ops)
+
+
+MODULE_AUTHOR("Frank Li <Frank.Li@nxp.com>");
+MODULE_DESCRIPTION("Freescale MU work as MSI controller driver");
+MODULE_LICENSE("GPL");
--
2.35.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 3/4] dt-bindings: irqchip: imx mu work as msi controller
2022-07-15 19:22 [PATCH v2 0/4] PCI EP driver support MSI doorbell from host Frank Li
2022-07-15 19:22 ` [PATCH v2 1/4] irqchip: allow pass down .pm field at IRQCHIP_PLATFORM_DRIVER_END Frank Li
2022-07-15 19:22 ` [PATCH v2 2/4] irqchip: imx mu worked as msi controller Frank Li
@ 2022-07-15 19:22 ` Frank Li
2022-07-15 23:06 ` Rob Herring
2022-07-15 19:22 ` [PATCH v2 4/4] pcie: endpoint: pci-epf-vntb: add endpoint msi support Frank Li
2022-07-15 21:14 ` [PATCH v2 0/4] PCI EP driver support MSI doorbell from host Bjorn Helgaas
4 siblings, 1 reply; 8+ messages in thread
From: Frank Li @ 2022-07-15 19:22 UTC (permalink / raw)
To: maz, tglx, robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer, kw,
bhelgaas
Cc: kernel, devicetree, linux-arm-kernel, linux-pci, peng.fan,
aisheng.dong, jdmason, kernel, festevam, linux-imx, kishon,
lorenzo.pieralisi, ntb
imx mu support generate irq by write a register.
provide msi controller support so other driver
can use it by standard msi interface.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
.../interrupt-controller/fsl,mu-msi.yaml | 88 +++++++++++++++++++
1 file changed, 88 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml
new file mode 100644
index 0000000000000..732ce770ac3bd
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX Messaging Unit (MU) work as msi controller
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+description: |
+ The Messaging Unit module enables two processors within the SoC to
+ communicate and coordinate by passing messages (e.g. data, status
+ and control) through the MU interface. The MU also provides the ability
+ for one processor to signal the other processor using interrupts.
+
+ Because the MU manages the messaging between processors, the MU uses
+ different clocks (from each side of the different peripheral buses).
+ Therefore, the MU must synchronize the accesses from one side to the
+ other. The MU accomplishes synchronization using two sets of matching
+ registers (Processor A-facing, Processor B-facing).
+
+ MU can work as msi interrupt controller to do doorbell
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx6sx-mu-msi
+ - fsl,imx7ulp-mu-msi
+ - fsl,imx8ulp-mu-msi
+ - fsl,imx8ulp-mu-msi-s4
+
+ reg:
+ minItems: 2
+
+ reg-names:
+ items:
+ - const: a
+ - const: b
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 2
+
+ power-domain-names:
+ items:
+ - const: a
+ - const: b
+
+ interrupt-controller: true
+
+ msi-controller: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - msi-controller
+ - interrupt-controller
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+
+ lsio_mu12: interrupt-controller@5d270000 {
+ compatible = "fsl,imx6sx-mu-msi";
+ msi-controller;
+ interrupt-controller;
+ reg = <0x5d270000 0x10000>, /* A side */
+ <0x5d300000 0x10000>; /* B side */
+ reg-names = "a", "b";
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd IMX_SC_R_MU_12A>,
+ <&pd IMX_SC_R_MU_12B>;
+ power-domain-names = "a", "b";
+ };
--
2.35.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 3/4] dt-bindings: irqchip: imx mu work as msi controller
2022-07-15 19:22 ` [PATCH v2 3/4] dt-bindings: irqchip: imx mu work " Frank Li
@ 2022-07-15 23:06 ` Rob Herring
0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2022-07-15 23:06 UTC (permalink / raw)
To: Frank Li
Cc: bhelgaas, robh+dt, lorenzo.pieralisi, peng.fan, ntb, kernel,
s.hauer, aisheng.dong, kw, linux-arm-kernel, kishon, maz,
festevam, shawnguo, tglx, krzysztof.kozlowski+dt, linux-pci,
devicetree, jdmason, linux-imx, kernel
On Fri, 15 Jul 2022 14:22:18 -0500, Frank Li wrote:
> imx mu support generate irq by write a register.
> provide msi controller support so other driver
> can use it by standard msi interface.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> .../interrupt-controller/fsl,mu-msi.yaml | 88 +++++++++++++++++++
> 1 file changed, 88 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.example.dtb: interrupt-controller@5d270000: '#interrupt-cells' is a dependency of 'interrupt-controller'
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.example.dtb: interrupt-controller@5d270000: '#interrupt-cells' is a dependency of 'interrupt-controller'
From schema: /usr/local/lib/python3.10/dist-packages/dtschema/schemas/interrupt-controller.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 4/4] pcie: endpoint: pci-epf-vntb: add endpoint msi support
2022-07-15 19:22 [PATCH v2 0/4] PCI EP driver support MSI doorbell from host Frank Li
` (2 preceding siblings ...)
2022-07-15 19:22 ` [PATCH v2 3/4] dt-bindings: irqchip: imx mu work " Frank Li
@ 2022-07-15 19:22 ` Frank Li
2022-07-15 21:06 ` Bjorn Helgaas
2022-07-15 21:14 ` [PATCH v2 0/4] PCI EP driver support MSI doorbell from host Bjorn Helgaas
4 siblings, 1 reply; 8+ messages in thread
From: Frank Li @ 2022-07-15 19:22 UTC (permalink / raw)
To: maz, tglx, robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer, kw,
bhelgaas
Cc: kernel, devicetree, linux-arm-kernel, linux-pci, peng.fan,
aisheng.dong, jdmason, kernel, festevam, linux-imx, kishon,
lorenzo.pieralisi, ntb
This patch add msi support for ntb endpoint(EP) side.
EP side driver query if system have msi controller.
Setup doorbell address according to struct msi_msg.
So PCIe host can write this doorbell address to EP
side's irq.
If no msi controller exist, failback software polling.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/pci/endpoint/functions/pci-epf-vntb.c | 134 +++++++++++++++---
1 file changed, 112 insertions(+), 22 deletions(-)
diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/endpoint/functions/pci-epf-vntb.c
index 1466dd1904175..dcaebcda4d7ad 100644
--- a/drivers/pci/endpoint/functions/pci-epf-vntb.c
+++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c
@@ -44,6 +44,7 @@
#include <linux/pci-epc.h>
#include <linux/pci-epf.h>
#include <linux/ntb.h>
+#include <linux/msi.h>
static struct workqueue_struct *kpcintb_workqueue;
@@ -143,6 +144,8 @@ struct epf_ntb {
void __iomem *vpci_mw_addr[MAX_MW];
struct delayed_work cmd_handler;
+
+ int msi_virqbase;
};
#define to_epf_ntb(epf_group) container_of((epf_group), struct epf_ntb, group)
@@ -253,7 +256,7 @@ static void epf_ntb_cmd_handler(struct work_struct *work)
ntb = container_of(work, struct epf_ntb, cmd_handler.work);
- for (i = 1; i < ntb->db_count; i++) {
+ for (i = 1; i < ntb->db_count && !ntb->epf_db_phy; i++) {
if (readl(ntb->epf_db + i * 4)) {
if (readl(ntb->epf_db + i * 4))
ntb->db |= 1 << (i - 1);
@@ -454,11 +457,9 @@ static int epf_ntb_config_spad_bar_alloc(struct epf_ntb *ntb)
ctrl->num_mws = ntb->num_mws;
ntb->spad_size = spad_size;
- ctrl->db_entry_size = 4;
-
for (i = 0; i < ntb->db_count; i++) {
ntb->reg->db_data[i] = 1 + i;
- ntb->reg->db_offset[i] = 0;
+ ntb->reg->db_offset[i] = 4 * i;
}
return 0;
@@ -509,6 +510,28 @@ static int epf_ntb_configure_interrupt(struct epf_ntb *ntb)
return 0;
}
+static int epf_ntb_db_size(struct epf_ntb *ntb)
+{
+ const struct pci_epc_features *epc_features;
+ size_t size = 4 * ntb->db_count;
+ u32 align;
+
+ epc_features = pci_epc_get_features(ntb->epf->epc,
+ ntb->epf->func_no,
+ ntb->epf->vfunc_no);
+ align = epc_features->align;
+
+ if (size < 128)
+ size = 128;
+
+ if (align)
+ size = ALIGN(size, align);
+ else
+ size = roundup_pow_of_two(size);
+
+ return size;
+}
+
/**
* epf_ntb_db_bar_init() - Configure Doorbell window BARs
* @ntb: NTB device that facilitates communication between HOST and vHOST
@@ -520,35 +543,33 @@ static int epf_ntb_db_bar_init(struct epf_ntb *ntb)
struct device *dev = &ntb->epf->dev;
int ret;
struct pci_epf_bar *epf_bar;
- void __iomem *mw_addr;
+ void __iomem *mw_addr = NULL;
enum pci_barno barno;
- size_t size = 4 * ntb->db_count;
+ size_t size;
epc_features = pci_epc_get_features(ntb->epf->epc,
ntb->epf->func_no,
ntb->epf->vfunc_no);
- align = epc_features->align;
- if (size < 128)
- size = 128;
-
- if (align)
- size = ALIGN(size, align);
- else
- size = roundup_pow_of_two(size);
+ size = epf_ntb_db_size(ntb);
barno = ntb->epf_ntb_bar[BAR_DB];
+ epf_bar = &ntb->epf->bar[barno];
- mw_addr = pci_epf_alloc_space(ntb->epf, size, barno, align, 0);
- if (!mw_addr) {
- dev_err(dev, "Failed to allocate OB address\n");
- return -ENOMEM;
+ if (!ntb->epf_db_phy) {
+ mw_addr = pci_epf_alloc_space(ntb->epf, size, barno, align, 0);
+ if (!mw_addr) {
+ dev_err(dev, "Failed to allocate OB address\n");
+ return -ENOMEM;
+ }
+ } else {
+ epf_bar->phys_addr = ntb->epf_db_phy;
+ epf_bar->barno = barno;
+ epf_bar->size = size;
}
ntb->epf_db = mw_addr;
- epf_bar = &ntb->epf->bar[barno];
-
ret = pci_epc_set_bar(ntb->epf->epc, ntb->epf->func_no, ntb->epf->vfunc_no, epf_bar);
if (ret) {
dev_err(dev, "Doorbell BAR set failed\n");
@@ -704,6 +725,74 @@ static int epf_ntb_init_epc_bar(struct epf_ntb *ntb)
return 0;
}
+static void epf_ntb_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
+{
+ struct epf_ntb *ntb = dev_get_drvdata(desc->dev);
+ struct epf_ntb_ctrl *reg = ntb->reg;
+ int size = epf_ntb_db_size(ntb);
+ u64 addr;
+
+ addr = msg->address_hi;
+ addr <<= 32;
+ addr |= msg->address_lo;
+
+ reg->db_data[desc->msi_index] = msg->data;
+
+ if (desc->msi_index == 0)
+ ntb->epf_db_phy = round_down(addr, size);
+
+ reg->db_offset[desc->msi_index] = addr - ntb->epf_db_phy;
+}
+
+static irqreturn_t epf_ntb_interrupt_handler(int irq, void *data)
+{
+ struct epf_ntb *ntb = data;
+ int index;
+
+ index = irq - ntb->msi_virqbase;
+ ntb->db |= 1 << (index - 1);
+ ntb_db_event(&ntb->ntb, index);
+
+ return IRQ_HANDLED;
+}
+
+static void epf_ntb_epc_msi_init(struct epf_ntb *ntb)
+{
+ struct irq_domain *domain;
+ struct device *dev = &ntb->epf->dev;
+ int ret;
+ int i;
+ int virq;
+
+ domain = dev_get_msi_domain(ntb->epf->epc->dev.parent);
+ if (!domain)
+ return;
+
+ dev_set_msi_domain(dev, domain);
+
+ if (platform_msi_domain_alloc_irqs(&ntb->epf->dev,
+ ntb->db_count,
+ epf_ntb_write_msi_msg)) {
+ dev_info(dev, "Can't allocate MSI, failure back to poll mode\n");
+ return;
+ }
+
+ dev_info(dev, "vntb use MSI as doorbell\n");
+
+ for (i = 0; i < ntb->db_count; i++) {
+ virq = msi_get_virq(dev, i);
+ ret = devm_request_irq(dev, virq,
+ epf_ntb_interrupt_handler, 0,
+ "ntb", ntb);
+
+ if (ret)
+ dev_err(dev, "request irq failure\n");
+
+ if (!i)
+ ntb->msi_virqbase = virq;
+ }
+}
+
/**
* epf_ntb_epc_init() - Initialize NTB interface
* @ntb: NTB device that facilitates communication between HOST and vHOST2
@@ -1299,14 +1388,15 @@ static int epf_ntb_bind(struct pci_epf *epf)
goto err_bar_alloc;
}
+ epf_set_drvdata(epf, ntb);
+ epf_ntb_epc_msi_init(ntb);
+
ret = epf_ntb_epc_init(ntb);
if (ret) {
dev_err(dev, "Failed to initialize EPC\n");
goto err_bar_alloc;
}
- epf_set_drvdata(epf, ntb);
-
pci_space[0] = (ntb->vntb_pid << 16) | ntb->vntb_vid;
pci_vntb_table[0].vendor = ntb->vntb_vid;
pci_vntb_table[0].device = ntb->vntb_pid;
--
2.35.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 4/4] pcie: endpoint: pci-epf-vntb: add endpoint msi support
2022-07-15 19:22 ` [PATCH v2 4/4] pcie: endpoint: pci-epf-vntb: add endpoint msi support Frank Li
@ 2022-07-15 21:06 ` Bjorn Helgaas
0 siblings, 0 replies; 8+ messages in thread
From: Bjorn Helgaas @ 2022-07-15 21:06 UTC (permalink / raw)
To: Frank Li, Jon Mason
Cc: maz, tglx, robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer, kw,
bhelgaas, kernel, devicetree, linux-arm-kernel, linux-pci,
peng.fan, aisheng.dong, kernel, festevam, linux-imx, kishon,
lorenzo.pieralisi, ntb
[+to Jon, since I guess he will apply or at least review this, not me]
On Fri, Jul 15, 2022 at 02:22:19PM -0500, Frank Li wrote:
> This patch add msi support for ntb endpoint(EP) side.
> EP side driver query if system have msi controller.
> Setup doorbell address according to struct msi_msg.
>
> So PCIe host can write this doorbell address to EP
> side's irq.
>
> If no msi controller exist, failback software polling.
s/This patch add/Add/
s/msi/MSI/ (several)
s/ntb/NTB/
s/irq/IRQ/
s/failback/fall back to/
Rewrap commit log to fill 75 columns to make it easier to read.
> +static int epf_ntb_db_size(struct epf_ntb *ntb)
> +{
> + const struct pci_epc_features *epc_features;
> + size_t size = 4 * ntb->db_count;
> + u32 align;
Replace tabs with spaces in these declarations , since that's what
code below does, e.g., in epf_ntb_db_bar_init(), etc.
> + dev_info(dev, "Can't allocate MSI, failure back to poll mode\n");
s/failure/fall/
> + return;
> + }
> +
> + dev_info(dev, "vntb use MSI as doorbell\n");
> + ret = devm_request_irq(dev, virq,
> + epf_ntb_interrupt_handler, 0,
> + "ntb", ntb);
> +
> + if (ret)
> + dev_err(dev, "request irq failure\n");
s/irq/IRQ/ (or spell out "devm_request_irq()").
Capitalize all messages or none of them. Match the prevailing style
of the file.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/4] PCI EP driver support MSI doorbell from host
2022-07-15 19:22 [PATCH v2 0/4] PCI EP driver support MSI doorbell from host Frank Li
` (3 preceding siblings ...)
2022-07-15 19:22 ` [PATCH v2 4/4] pcie: endpoint: pci-epf-vntb: add endpoint msi support Frank Li
@ 2022-07-15 21:14 ` Bjorn Helgaas
4 siblings, 0 replies; 8+ messages in thread
From: Bjorn Helgaas @ 2022-07-15 21:14 UTC (permalink / raw)
To: Frank Li
Cc: maz, tglx, robh+dt, krzysztof.kozlowski+dt, shawnguo, s.hauer, kw,
bhelgaas, kernel, devicetree, linux-arm-kernel, linux-pci,
peng.fan, aisheng.dong, jdmason, kernel, festevam, linux-imx,
kishon, lorenzo.pieralisi, ntb
On Fri, Jul 15, 2022 at 02:22:15PM -0500, Frank Li wrote:
>
> ┌───────┐ ┌──────────┐
> │ │ │ │
> ┌─────────────┐ │ │ │ PCI Host │
> │ MSI │◄┐ │ │ │ │
> │ Controller │ │ │ │ │ │
> └─────────────┘ └─┼───────┼──────────┼─Bar0 │
> │ PCI │ │ Bar1 │
> │ Func │ │ Bar2 │
> │ │ │ Bar3 │
> │ │ │ Bar4 │
> │ ├─────────►│ │
> └───────┘ └──────────┘
Nice diagram and explanation. I suggest rewrapping to fit in 75
columns and including in one of the patches, probably the
pci-epf-vntb.c one. Then it will be more likely to make it to the git
history where it will be useful.
> Many PCI controllers provided Endpoint functions.
> Generally PCI endpoint is hardware, which is not running a rich OS, like linux.
>
> But Linux also supports endpoint functions. PCI Host write bar<n> space like
> write to memory. The EP side can't know memory changed by the Host driver.
>
> PCI Spec has not defined a standard method to do that. Only define MSI(x) to let
> EP notified RC status change.
>
> The basic idea is to trigger an irq when PCI RC writes to a memory address. That's
> what MSI controller provided. EP drivers just need to request a platform MSI interrupt,
> struct msi_msg *msg will pass down a memory address and data. EP driver will
> map such memory address to one of PCI bar<n>. Host just writes such an address to
> trigger EP side irq.
>
> If system have gic-its, only need update PCI EP side driver. But i.MX have not chip
> support gic-ites yet. So we have to use MU to simulate a MSI controller. Although
> only 4 MSI irqs are simulated, it matched vntd network requirmenent.
>
> After enable MSI, ping delay reduce < 1ms from ~8ms
>
> irqchip: imx mu worked as msi controller:
> let imx mu worked as MSI controllers. Although IP is not design as MSI controller,
> we still can use it if limiated irq number to 4.
>
> pcie: endpoint: pci-epf-vntb: add endpoint msi support
> Based on ntb-next branch. https://github.com/jonmason/ntb/commits/ntb-next
> Using MSI as door bell registers
>
> i.MX EP function driver is upstreaming by Richard Zhu.
> Some dts change missed at this patches. below is reference dts change
s/bar/BAR/ (several)
s/irq/IRQ/ (several)
s/irqs/IRQs/
s/msi/MSI/
s/gic-ites/? (capitalize if it's an acronym)
s/requirmenent/requirement/
s/limiated/limited/
You use both "gic-its" and "gic-ites". I assume they should be the
same.
Not sure what "vntd" refers to. Capitalize if it's an acronym.
> --- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
> @@ -160,5 +160,6 @@ pcieb_ep: pcie_ep@5f010000 {
> num-ib-windows = <6>;
> num-ob-windows = <6>;
> status = "disabled";
> + msi-parent = <&lsio_mu12>;
> };
>
> --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> @@ -172,6 +172,19 @@ lsio_mu6: mailbox@5d210000 {
> status = "disabled";
> };
>
> + lsio_mu12: mailbox@5d270000 {
> + compatible = "fsl,imx6sx-mu-msi";
> + msi-controller;
> + interrupt-controller;
> + reg = <0x5d270000 0x10000>, /* A side */
> + <0x5d300000 0x10000>; /* B side */
> + reg-names = "a", "b";
> + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&pd IMX_SC_R_MU_12A>,
> + <&pd IMX_SC_R_MU_12B>;
> + power-domain-names = "a", "b";
> + };
> +
>
> Change Log
> - from V1 to V2
> Fixed fsl,mu-msi.yaml's problem
> Fixed irq-imx-mu-msi.c problem according Marc Zyngier's feeback
> Added a new patch to allow pass down .pm by IRQCHIP_PLATFORM_DRIVER_END
>
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread