* [PATCH 1/5] arm64: dts: renesas: r9a07g044: Add IRQC node to SoC DTSI
2022-07-18 19:56 [PATCH 0/5] Add IRQC support to Renesas RZ/G2L and RZ/V2L SoC Lad Prabhakar
@ 2022-07-18 19:56 ` Lad Prabhakar
2022-07-21 10:38 ` Geert Uytterhoeven
2022-07-18 19:56 ` [PATCH 2/5] arm64: dts: renesas: r9a07g044: Update pinctrl node to handle GPIO interrupts Lad Prabhakar
` (3 subsequent siblings)
4 siblings, 1 reply; 16+ messages in thread
From: Lad Prabhakar @ 2022-07-18 19:56 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
linux-renesas-soc, devicetree
Cc: linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Add IRQC node to R9A07G044 (RZ/G2L) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 55 ++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 3652e511160f..46fb3d83592a 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -646,6 +646,61 @@ pinctrl: pinctrl@11030000 {
<&cpg R9A07G044_GPIO_SPARE_RESETN>;
};
+ irqc: interrupt-controller@110a0000 {
+ compatible = "renesas,r9a07g044-irqc",
+ "renesas,rzg2l-irqc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0x110a0000 0 0x10000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
+ <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
+ clock-names = "clk", "pclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_IA55_RESETN>;
+ };
+
dmac: dma-controller@11820000 {
compatible = "renesas,r9a07g044-dmac",
"renesas,rz-dmac";
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 1/5] arm64: dts: renesas: r9a07g044: Add IRQC node to SoC DTSI
2022-07-18 19:56 ` [PATCH 1/5] arm64: dts: renesas: r9a07g044: Add IRQC node to SoC DTSI Lad Prabhakar
@ 2022-07-21 10:38 ` Geert Uytterhoeven
0 siblings, 0 replies; 16+ messages in thread
From: Geert Uytterhoeven @ 2022-07-21 10:38 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Prabhakar, Biju Das
On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add IRQC node to R9A07G044 (RZ/G2L) SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.21.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/5] arm64: dts: renesas: r9a07g044: Update pinctrl node to handle GPIO interrupts
2022-07-18 19:56 [PATCH 0/5] Add IRQC support to Renesas RZ/G2L and RZ/V2L SoC Lad Prabhakar
2022-07-18 19:56 ` [PATCH 1/5] arm64: dts: renesas: r9a07g044: Add IRQC node to SoC DTSI Lad Prabhakar
@ 2022-07-18 19:56 ` Lad Prabhakar
2022-07-21 10:41 ` Geert Uytterhoeven
2022-07-18 19:56 ` [PATCH 3/5] arm64: dts: renesas: r9a07g054: Add IRQC node to SoC DTSI Lad Prabhakar
` (2 subsequent siblings)
4 siblings, 1 reply; 16+ messages in thread
From: Lad Prabhakar @ 2022-07-18 19:56 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
linux-renesas-soc, devicetree
Cc: linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Add required properties in pinctrl node to handle GPIO interrupts.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 46fb3d83592a..cfdcca1cf9c6 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -638,6 +638,10 @@ pinctrl: pinctrl@11030000 {
reg = <0 0x11030000 0 0x10000>;
gpio-controller;
#gpio-cells = <2>;
+ #address-cells = <2>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&irqc>;
+ interrupt-controller;
gpio-ranges = <&pinctrl 0 0 392>;
clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
power-domains = <&cpg>;
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 2/5] arm64: dts: renesas: r9a07g044: Update pinctrl node to handle GPIO interrupts
2022-07-18 19:56 ` [PATCH 2/5] arm64: dts: renesas: r9a07g044: Update pinctrl node to handle GPIO interrupts Lad Prabhakar
@ 2022-07-21 10:41 ` Geert Uytterhoeven
0 siblings, 0 replies; 16+ messages in thread
From: Geert Uytterhoeven @ 2022-07-21 10:41 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Prabhakar, Biju Das
On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add required properties in pinctrl node to handle GPIO interrupts.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.21.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/5] arm64: dts: renesas: r9a07g054: Add IRQC node to SoC DTSI
2022-07-18 19:56 [PATCH 0/5] Add IRQC support to Renesas RZ/G2L and RZ/V2L SoC Lad Prabhakar
2022-07-18 19:56 ` [PATCH 1/5] arm64: dts: renesas: r9a07g044: Add IRQC node to SoC DTSI Lad Prabhakar
2022-07-18 19:56 ` [PATCH 2/5] arm64: dts: renesas: r9a07g044: Update pinctrl node to handle GPIO interrupts Lad Prabhakar
@ 2022-07-18 19:56 ` Lad Prabhakar
2022-07-21 10:39 ` Geert Uytterhoeven
2022-07-18 19:56 ` [PATCH 4/5] arm64: dts: renesas: r9a07g054: Update pinctrl node to handle GPIO interrupts Lad Prabhakar
2022-07-18 19:56 ` [PATCH 5/5] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1} Lad Prabhakar
4 siblings, 1 reply; 16+ messages in thread
From: Lad Prabhakar @ 2022-07-18 19:56 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
linux-renesas-soc, devicetree
Cc: linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Add IRQC node to R9A07G054 (RZ/V2L) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 55 ++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 4d6b9d7684c9..4b8a09abfc7f 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -652,6 +652,61 @@ pinctrl: pinctrl@11030000 {
<&cpg R9A07G054_GPIO_SPARE_RESETN>;
};
+ irqc: interrupt-controller@110a0000 {
+ compatible = "renesas,r9a07g054-irqc",
+ "renesas,rzg2l-irqc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0x110a0000 0 0x10000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>,
+ <&cpg CPG_MOD R9A07G054_IA55_PCLK>;
+ clock-names = "clk", "pclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_IA55_RESETN>;
+ };
+
dmac: dma-controller@11820000 {
compatible = "renesas,r9a07g054-dmac",
"renesas,rz-dmac";
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 3/5] arm64: dts: renesas: r9a07g054: Add IRQC node to SoC DTSI
2022-07-18 19:56 ` [PATCH 3/5] arm64: dts: renesas: r9a07g054: Add IRQC node to SoC DTSI Lad Prabhakar
@ 2022-07-21 10:39 ` Geert Uytterhoeven
0 siblings, 0 replies; 16+ messages in thread
From: Geert Uytterhoeven @ 2022-07-21 10:39 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Prabhakar, Biju Das
On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add IRQC node to R9A07G054 (RZ/V2L) SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.21.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 4/5] arm64: dts: renesas: r9a07g054: Update pinctrl node to handle GPIO interrupts
2022-07-18 19:56 [PATCH 0/5] Add IRQC support to Renesas RZ/G2L and RZ/V2L SoC Lad Prabhakar
` (2 preceding siblings ...)
2022-07-18 19:56 ` [PATCH 3/5] arm64: dts: renesas: r9a07g054: Add IRQC node to SoC DTSI Lad Prabhakar
@ 2022-07-18 19:56 ` Lad Prabhakar
2022-07-21 10:41 ` Geert Uytterhoeven
2022-07-18 19:56 ` [PATCH 5/5] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1} Lad Prabhakar
4 siblings, 1 reply; 16+ messages in thread
From: Lad Prabhakar @ 2022-07-18 19:56 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
linux-renesas-soc, devicetree
Cc: linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Add required properties in pinctrl node to handle GPIO interrupts.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 4b8a09abfc7f..24611e4a7913 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -644,6 +644,10 @@ pinctrl: pinctrl@11030000 {
reg = <0 0x11030000 0 0x10000>;
gpio-controller;
#gpio-cells = <2>;
+ #address-cells = <2>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&irqc>;
+ interrupt-controller;
gpio-ranges = <&pinctrl 0 0 392>;
clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>;
power-domains = <&cpg>;
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 4/5] arm64: dts: renesas: r9a07g054: Update pinctrl node to handle GPIO interrupts
2022-07-18 19:56 ` [PATCH 4/5] arm64: dts: renesas: r9a07g054: Update pinctrl node to handle GPIO interrupts Lad Prabhakar
@ 2022-07-21 10:41 ` Geert Uytterhoeven
0 siblings, 0 replies; 16+ messages in thread
From: Geert Uytterhoeven @ 2022-07-21 10:41 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Prabhakar, Biju Das
On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add required properties in pinctrl node to handle GPIO interrupts.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.21.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 5/5] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1}
2022-07-18 19:56 [PATCH 0/5] Add IRQC support to Renesas RZ/G2L and RZ/V2L SoC Lad Prabhakar
` (3 preceding siblings ...)
2022-07-18 19:56 ` [PATCH 4/5] arm64: dts: renesas: r9a07g054: Update pinctrl node to handle GPIO interrupts Lad Prabhakar
@ 2022-07-18 19:56 ` Lad Prabhakar
2022-07-21 10:46 ` Geert Uytterhoeven
4 siblings, 1 reply; 16+ messages in thread
From: Lad Prabhakar @ 2022-07-18 19:56 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
linux-renesas-soc, devicetree
Cc: linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0
and ETH1 respectively.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
index 9410796c8ad6..f15d093fc6de 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
@@ -94,6 +94,8 @@ phy0: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
+ interrupt-parent = <&irqc>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
@@ -120,6 +122,8 @@ phy1: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
+ interrupt-parent = <&irqc>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
@@ -171,7 +175,8 @@ eth0_pins: eth0 {
<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
- <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
+ <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
+ <RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */
};
eth1_pins: eth1 {
@@ -189,7 +194,8 @@ eth1_pins: eth1 {
<RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
<RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
<RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
- <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
+ <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */
+ <RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */
};
gpio-sd0-pwr-en-hog {
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 5/5] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1}
2022-07-18 19:56 ` [PATCH 5/5] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1} Lad Prabhakar
@ 2022-07-21 10:46 ` Geert Uytterhoeven
2022-07-21 11:06 ` Lad, Prabhakar
0 siblings, 1 reply; 16+ messages in thread
From: Geert Uytterhoeven @ 2022-07-21 10:46 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Prabhakar, Biju Das
Hi Prabhakar,
On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0
> and ETH1 respectively.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
> @@ -94,6 +94,8 @@ phy0: ethernet-phy@7 {
> compatible = "ethernet-phy-id0022.1640",
> "ethernet-phy-ieee802.3-c22";
> reg = <7>;
> + interrupt-parent = <&irqc>;
> + interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
2?
"The first cell should contain external interrupt number (IRQ0-7)"
> rxc-skew-psec = <2400>;
> txc-skew-psec = <2400>;
> rxdv-skew-psec = <0>;
> @@ -120,6 +122,8 @@ phy1: ethernet-phy@7 {
> compatible = "ethernet-phy-id0022.1640",
> "ethernet-phy-ieee802.3-c22";
> reg = <7>;
> + interrupt-parent = <&irqc>;
> + interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
3?
> rxc-skew-psec = <2400>;
> txc-skew-psec = <2400>;
> rxdv-skew-psec = <0>;
> @@ -171,7 +175,8 @@ eth0_pins: eth0 {
> <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
> <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
> <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
> - <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
> + <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
> + <RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */
> };
>
> eth1_pins: eth1 {
> @@ -189,7 +194,8 @@ eth1_pins: eth1 {
> <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
> <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
> <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
> - <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
> + <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */
> + <RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */
> };
>
> gpio-sd0-pwr-en-hog {
> --
> 2.25.1
>
--
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 5/5] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1}
2022-07-21 10:46 ` Geert Uytterhoeven
@ 2022-07-21 11:06 ` Lad, Prabhakar
2022-07-21 11:43 ` Geert Uytterhoeven
0 siblings, 1 reply; 16+ messages in thread
From: Lad, Prabhakar @ 2022-07-21 11:06 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Biju Das
Hi Geert,
Thank you for the review.
On Thu, Jul 21, 2022 at 11:47 AM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0
> > and ETH1 respectively.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
> > @@ -94,6 +94,8 @@ phy0: ethernet-phy@7 {
> > compatible = "ethernet-phy-id0022.1640",
> > "ethernet-phy-ieee802.3-c22";
> > reg = <7>;
> > + interrupt-parent = <&irqc>;
> > + interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
>
> 2?
>
IRQ2 = SPI 3, the driver expects the SPI number and is used as index
[0] to map the interrupt in the GIC.
[0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/irqchip/irq-renesas-rzg2l.c?h=next-20220720#n291
> "The first cell should contain external interrupt number (IRQ0-7)"
>
Probably I need to reword this to "The first cell should contain the
SPI number for IRQ0-7/NMI interrupt lines" ?
> > rxc-skew-psec = <2400>;
> > txc-skew-psec = <2400>;
> > rxdv-skew-psec = <0>;
> > @@ -120,6 +122,8 @@ phy1: ethernet-phy@7 {
> > compatible = "ethernet-phy-id0022.1640",
> > "ethernet-phy-ieee802.3-c22";
> > reg = <7>;
> > + interrupt-parent = <&irqc>;
> > + interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
>
> 3?
>
IRQ3 = SPI 4
Cheers,
Prabhakar
> > rxc-skew-psec = <2400>;
> > txc-skew-psec = <2400>;
> > rxdv-skew-psec = <0>;
> > @@ -171,7 +175,8 @@ eth0_pins: eth0 {
> > <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
> > <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
> > <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
> > - <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
> > + <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
> > + <RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */
> > };
> >
> > eth1_pins: eth1 {
> > @@ -189,7 +194,8 @@ eth1_pins: eth1 {
> > <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
> > <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
> > <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
> > - <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
> > + <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */
> > + <RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */
> > };
> >
> > gpio-sd0-pwr-en-hog {
> > --
> > 2.25.1
> >
>
>
> --
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 5/5] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1}
2022-07-21 11:06 ` Lad, Prabhakar
@ 2022-07-21 11:43 ` Geert Uytterhoeven
2022-07-21 11:54 ` Lad, Prabhakar
0 siblings, 1 reply; 16+ messages in thread
From: Geert Uytterhoeven @ 2022-07-21 11:43 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Biju Das
Hi Prabhakar,
On Thu, Jul 21, 2022 at 1:07 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Thu, Jul 21, 2022 at 11:47 AM Geert Uytterhoeven
> <geert@linux-m68k.org> wrote:
> > On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0
> > > and ETH1 respectively.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
> > > @@ -94,6 +94,8 @@ phy0: ethernet-phy@7 {
> > > compatible = "ethernet-phy-id0022.1640",
> > > "ethernet-phy-ieee802.3-c22";
> > > reg = <7>;
> > > + interrupt-parent = <&irqc>;
> > > + interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> >
> > 2?
> >
> IRQ2 = SPI 3, the driver expects the SPI number and is used as index
> [0] to map the interrupt in the GIC.
>
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/irqchip/irq-renesas-rzg2l.c?h=next-20220720#n291
Using the SPI number sounds strange to me, as the consumer
(Ethernet PHY) is linked to the IRQC, not to the GIC directly.
> > "The first cell should contain external interrupt number (IRQ0-7)"
> >
> Probably I need to reword this to "The first cell should contain the
> SPI number for IRQ0-7/NMI interrupt lines" ?
Oh, so zero is the NMI?
And 1-8 are IRQ0-7.
All of this should be documented in the bindings.
Probably you want to document the parent interrupts:
- First entry is NMI,
- Next 8 entries are IRQ0-7,
- Next 32 entries are TINT0-31.
Currently it's a flat list.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 5/5] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1}
2022-07-21 11:43 ` Geert Uytterhoeven
@ 2022-07-21 11:54 ` Lad, Prabhakar
2022-07-21 11:59 ` Geert Uytterhoeven
0 siblings, 1 reply; 16+ messages in thread
From: Lad, Prabhakar @ 2022-07-21 11:54 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Biju Das
Hi Geert,
On Thu, Jul 21, 2022 at 12:43 PM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Thu, Jul 21, 2022 at 1:07 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Thu, Jul 21, 2022 at 11:47 AM Geert Uytterhoeven
> > <geert@linux-m68k.org> wrote:
> > > On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0
> > > > and ETH1 respectively.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Thanks for your patch!
> > >
> > > > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
> > > > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
> > > > @@ -94,6 +94,8 @@ phy0: ethernet-phy@7 {
> > > > compatible = "ethernet-phy-id0022.1640",
> > > > "ethernet-phy-ieee802.3-c22";
> > > > reg = <7>;
> > > > + interrupt-parent = <&irqc>;
> > > > + interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> > >
> > > 2?
> > >
> > IRQ2 = SPI 3, the driver expects the SPI number and is used as index
> > [0] to map the interrupt in the GIC.
> >
> > [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/irqchip/irq-renesas-rzg2l.c?h=next-20220720#n291
>
> Using the SPI number sounds strange to me, as the consumer
> (Ethernet PHY) is linked to the IRQC, not to the GIC directly.
>
Right, are you suggesting that I tweak the driver? The other problem
is how do we differentiate NMI and IRQ0? How about we add macros for
IRQ0-7 and use them in the DTS?
> > > "The first cell should contain external interrupt number (IRQ0-7)"
> > >
> > Probably I need to reword this to "The first cell should contain the
> > SPI number for IRQ0-7/NMI interrupt lines" ?
>
> Oh, so zero is the NMI?
> And 1-8 are IRQ0-7.
>
Yes that's right.
> All of this should be documented in the bindings.
>
> Probably you want to document the parent interrupts:
> - First entry is NMI,
> - Next 8 entries are IRQ0-7,
> - Next 32 entries are TINT0-31.
> Currently it's a flat list.
>
Agreed, I will update that.
Cheers,
Prabhakar
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 5/5] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1}
2022-07-21 11:54 ` Lad, Prabhakar
@ 2022-07-21 11:59 ` Geert Uytterhoeven
2022-07-21 12:06 ` Lad, Prabhakar
0 siblings, 1 reply; 16+ messages in thread
From: Geert Uytterhoeven @ 2022-07-21 11:59 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Biju Das
Hi Prabhakar,
On Thu, Jul 21, 2022 at 1:55 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Thu, Jul 21, 2022 at 12:43 PM Geert Uytterhoeven
> <geert@linux-m68k.org> wrote:
> > On Thu, Jul 21, 2022 at 1:07 PM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> > > On Thu, Jul 21, 2022 at 11:47 AM Geert Uytterhoeven
> > > <geert@linux-m68k.org> wrote:
> > > > On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > > > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0
> > > > > and ETH1 respectively.
> > > > >
> > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Thanks for your patch!
> > > >
> > > > > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
> > > > > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
> > > > > @@ -94,6 +94,8 @@ phy0: ethernet-phy@7 {
> > > > > compatible = "ethernet-phy-id0022.1640",
> > > > > "ethernet-phy-ieee802.3-c22";
> > > > > reg = <7>;
> > > > > + interrupt-parent = <&irqc>;
> > > > > + interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> > > >
> > > > 2?
> > > >
> > > IRQ2 = SPI 3, the driver expects the SPI number and is used as index
> > > [0] to map the interrupt in the GIC.
> > >
> > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/irqchip/irq-renesas-rzg2l.c?h=next-20220720#n291
> >
> > Using the SPI number sounds strange to me, as the consumer
> > (Ethernet PHY) is linked to the IRQC, not to the GIC directly.
> >
> Right, are you suggesting that I tweak the driver? The other problem
> is how do we differentiate NMI and IRQ0? How about we add macros for
> IRQ0-7 and use them in the DTS?
>
> > > > "The first cell should contain external interrupt number (IRQ0-7)"
> > > >
> > > Probably I need to reword this to "The first cell should contain the
> > > SPI number for IRQ0-7/NMI interrupt lines" ?
> >
> > Oh, so zero is the NMI?
> > And 1-8 are IRQ0-7.
> >
> Yes that's right.
I don't think it was ever mentioned that the NMI was exposed, too.
Using macros sounds fine to me.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 5/5] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1}
2022-07-21 11:59 ` Geert Uytterhoeven
@ 2022-07-21 12:06 ` Lad, Prabhakar
0 siblings, 0 replies; 16+ messages in thread
From: Lad, Prabhakar @ 2022-07-21 12:06 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Biju Das
Hi Geert,
On Thu, Jul 21, 2022 at 12:59 PM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Thu, Jul 21, 2022 at 1:55 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Thu, Jul 21, 2022 at 12:43 PM Geert Uytterhoeven
> > <geert@linux-m68k.org> wrote:
> > > On Thu, Jul 21, 2022 at 1:07 PM Lad, Prabhakar
> > > <prabhakar.csengg@gmail.com> wrote:
> > > > On Thu, Jul 21, 2022 at 11:47 AM Geert Uytterhoeven
> > > > <geert@linux-m68k.org> wrote:
> > > > > On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar
> > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > > > > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0
> > > > > > and ETH1 respectively.
> > > > > >
> > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > Thanks for your patch!
> > > > >
> > > > > > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
> > > > > > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
> > > > > > @@ -94,6 +94,8 @@ phy0: ethernet-phy@7 {
> > > > > > compatible = "ethernet-phy-id0022.1640",
> > > > > > "ethernet-phy-ieee802.3-c22";
> > > > > > reg = <7>;
> > > > > > + interrupt-parent = <&irqc>;
> > > > > > + interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> > > > >
> > > > > 2?
> > > > >
> > > > IRQ2 = SPI 3, the driver expects the SPI number and is used as index
> > > > [0] to map the interrupt in the GIC.
> > > >
> > > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/irqchip/irq-renesas-rzg2l.c?h=next-20220720#n291
> > >
> > > Using the SPI number sounds strange to me, as the consumer
> > > (Ethernet PHY) is linked to the IRQC, not to the GIC directly.
> > >
> > Right, are you suggesting that I tweak the driver? The other problem
> > is how do we differentiate NMI and IRQ0? How about we add macros for
> > IRQ0-7 and use them in the DTS?
> >
> > > > > "The first cell should contain external interrupt number (IRQ0-7)"
> > > > >
> > > > Probably I need to reword this to "The first cell should contain the
> > > > SPI number for IRQ0-7/NMI interrupt lines" ?
> > >
> > > Oh, so zero is the NMI?
> > > And 1-8 are IRQ0-7.
> > >
> > Yes that's right.
>
> I don't think it was ever mentioned that the NMI was exposed, too.
>
Sorry for not making this clearer.
> Using macros sounds fine to me.
>
Ok, I will send a v2 (just this patch alone) with the macros added as
a separate patch in rzg2l-pinctrl.h?
Cheers,
Prabhakar
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
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