* [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink
@ 2022-07-15 21:59 Sean Anderson
2022-07-15 21:59 ` [PATCH net-next v3 01/47] dt-bindings: phy: Add Lynx 10G phy binding Sean Anderson
` (10 more replies)
0 siblings, 11 replies; 30+ messages in thread
From: Sean Anderson @ 2022-07-15 21:59 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Madalin Bucur, netdev
Cc: Paolo Abeni, Eric Dumazet, linux-arm-kernel, Russell King,
linux-kernel, Sean Anderson, Alexandru Marginean, Andrew Lunn,
Benjamin Herrenschmidt, Heiner Kallweit, Ioana Ciornei,
Jonathan Corbet, Kishon Vijay Abraham I, Krzysztof Kozlowski,
Li Yang, Michael Ellerman, Paul Mackerras, Rob Herring, Shawn Guo,
Vinod Koul, Vladimir Oltean, devicetree, linux-doc, linux-phy,
linuxppc-dev
This series converts the DPAA driver to phylink. Additionally,
it also adds a serdes driver to allow for dynamic reconfiguration
between 1g and 10g interfaces (such as in an SFP+ slot). These changes
are submitted together for this RFT, but they will eventually be
submitted separately to the appropriate subsystem maintainers.
I have tried to maintain backwards compatibility with existing device
trees whereever possible. However, one area where I was unable to
achieve this was with QSGMII. Please refer to patch 4 for details.
All mac drivers have now been converted. I would greatly appreciate if
anyone has QorIQ boards they can test/debug this series on. I only have an
LS1046ARDB. Everything but QSGMII should work without breakage; QSGMII
needs patches 42 and 43.
The serdes driver is mostly functional (except for XFI). This series
only adds support for the LS1046ARDB SerDes (and untested LS1088ARDB),
but it should be fairly straightforward to add support for other SoCs
and boards (see Documentation/driver-api/phy/qoriq.rst).
This is the last spin of this series with all patches included. After next
week (depending on feedback) I will resend the patches broken up as
follows:
- 5: 1000BASE-KX support
- 1, 6, 44, 45: Lynx 10G support
- 7-10, 12-14: Phy rate adaptation support
- 2-4, 15-43, 46, 47: DPAA phylink conversion
Patches 15-19 were first submitted as [1].
[1] https://lore.kernel.org/netdev/20220531195851.1592220-1-sean.anderson@seco.com/
Changes in v3:
- Manually expand yaml references
- Add mode configuration to device tree
- Expand pcs-handle to an array
- Incorperate some minor changes into the first FMan binding commit
- Add vendor prefix 'fsl,' to rgmii and mii properties.
- Set maxItems for pcs-names
- Remove phy-* properties from example because dt-schema complains and I
can't be bothered to figure out how to make it work.
- Add pcs-handle as a preferred version of pcsphy-handle
- Deprecate pcsphy-handle
- Remove mii/rmii properties
- Add 1000BASE-KX interface mode
- Rename remaining references to QorIQ SerDes to Lynx 10G
- Fix PLL enable sequence by waiting for our reset request to be cleared
before continuing. Do the same for the lock, even though it isn't as
critical. Because we will delay for 1.5ms on average, use prepare
instead of enable so we can sleep.
- Document the status of each protocol
- Fix offset of several bitfields in RECR0
- Take into account PLLRST_B, SDRST_B, and SDEN when considering whether
a PLL is "enabled."
- Only power off unused lanes.
- Split mode lane mask into first/last lane (like group)
- Read modes from device tree
- Use caps to determine whether KX/KR are supported
- Move modes to lynx_priv
- Ensure that the protocol controller is not already in-use when we try
to configure a new mode. This should only occur if the device tree is
misconfigured (e.g. when QSGMII is selected on two lanes but there is
only one QSGMII controller).
- Split PLL drivers off into their own file
- Add clock for "ext_dly" instead of writing the bit directly (and
racing with any clock code).
- Use kasprintf instead of open-coding the snprintf dance
- Support 1000BASE-KX in lynx_lookup_proto. This still requires PCS
support, so nothing is truly "enabled" yet.
- Add support for phy rate adaptation
- Support differing link speeds and interface speeds
- Adjust advertisement based on rate adaptation
- Adjust link settings based on rate adaptation
- Add support for CRS-based rate adaptation
- Add support for AQR115
- Add some additional phy interfaces
- Add support for aquantia rate adaptation
- Put the PCS mdiodev only after we are done with it (since the PCS
does not perform a get itself).
- Remove _return label from memac_initialization in favor of returning
directly
- Fix grabbing the default PCS not checking for -ENODATA from
of_property_match_string
- Set DTSEC_ECNTRL_R100M in dtsec_link_up instead of dtsec_mac_config
- Remove rmii/mii properties
- Replace 1000Base... with 1000BASE... to match IEEE capitalization
- Add compatibles for QSGMII PCSs
- Split arm and powerpcs dts updates
- Describe modes in device tree
- ls1088a: Add serdes bindings
Changes in v2:
- Rename to fsl,lynx-10g.yaml
- Refer to the device in the documentation, rather than the binding
- Move compatible first
- Document phy cells in the description
- Allow a value of 1 for phy-cells. This allows for compatibility with
the similar (but according to Ioana Ciornei different enough) lynx-28g
binding.
- Remove minItems
- Use list for clock-names
- Fix example binding having too many cells in regs
- Add #clock-cells. This will allow using assigned-clocks* to configure
the PLLs.
- Document the structure of the compatible strings
- Convert FMan MAC bindings to yaml
- Better document how we select which PCS to use in the default case
- Rename driver to Lynx 10G (etc.)
- Fix not clearing group->pll after disabling it
- Support 1 and 2 phy-cells
- Power off lanes during probe
- Clear SGMIIaCR1_PCS_EN during probe
- Rename LYNX_PROTO_UNKNOWN to LYNX_PROTO_NONE
- Handle 1000BASE-KX in lynx_proto_mode_prep
- Remove some unused variables
- Fix prototype for dtsec_initialization
- Fix warning if sizeof(void *) != sizeof(resource_size_t)
- Specify type of mac_dev for exception_cb
- Add helper for sanity checking cgr ops
- Add CGR update function
- Adjust queue depth on rate change
- Move PCS_LYNX dependency to fman Kconfig
- Remove unused variable slow_10g_if
- Restrict valid link modes based on the phy interface. This is easier
to set up, and mostly captures what I intended to do the first time.
We now have a custom validate which restricts half-duplex for some SoCs
for RGMII, but generally just uses the default phylink validate.
- Configure the SerDes in enable/disable
- Properly implement all ethtool ops and ioctls. These were mostly
stubbed out just enough to compile last time.
- Convert 10GEC and dTSEC as well
- Fix capitalization of mEMAC in commit messages
- Add nodes for QSGMII PCSs
- Add nodes for QSGMII PCSs
- Use one phy cell for SerDes1, since no lanes can be grouped
- Disable SerDes by default to prevent breaking boards inadvertently.
Sean Anderson (47):
dt-bindings: phy: Add Lynx 10G phy binding
dt-bindings: net: Expand pcs-handle to an array
dt-bindings: net: Convert FMan MAC bindings to yaml
dt-bindings: net: fman: Add additional interface properties
net: phy: Add 1000BASE-KX interface mode
[RFT] phy: fsl: Add Lynx 10G SerDes driver
net: phy: Add support for rate adaptation
net: phylink: Support differing link speeds and interface speeds
net: phylink: Adjust advertisement based on rate adaptation
net: phylink: Adjust link settings based on rate adaptation
[RFC] net: phylink: Add support for CRS-based rate adaptation
net: phy: aquantia: Add support for AQR115
net: phy: aquantia: Add some additional phy interfaces
net: phy: aquantia: Add support for rate adaptation
net: fman: Convert to SPDX identifiers
net: fman: Don't pass comm_mode to enable/disable
net: fman: Store en/disable in mac_device instead of mac_priv_s
net: fman: dtsec: Always gracefully stop/start
net: fman: Get PCS node in per-mac init
net: fman: Store initialization function in match data
net: fman: Move struct dev to mac_device
net: fman: Configure fixed link in memac_initialization
net: fman: Export/rename some common functions
net: fman: memac: Use params instead of priv for max_speed
net: fman: Move initialization to mac-specific files
net: fman: Mark mac methods static
net: fman: Inline several functions into initialization
net: fman: Remove internal_phy_node from params
net: fman: Map the base address once
net: fman: Pass params directly to mac init
net: fman: Use mac_dev for some params
net: fman: Specify type of mac_dev for exception_cb
net: fman: Clean up error handling
net: fman: Change return type of disable to void
net: dpaa: Use mac_dev variable in dpaa_netdev_init
soc: fsl: qbman: Add helper for sanity checking cgr ops
soc: fsl: qbman: Add CGR update function
net: dpaa: Adjust queue depth on rate change
net: fman: memac: Add serdes support
net: fman: memac: Use lynx pcs driver
[RFT] net: dpaa: Convert to phylink
powerpc: dts: qoriq: Add nodes for QSGMII PCSs
arm64: dts: layerscape: Add nodes for QSGMII PCSs
arm64: dts: ls1046a: Add serdes bindings
arm64: dts: ls1088a: Add serdes bindings
arm64: dts: ls1046ardb: Add serdes bindings
[WIP] arm64: dts: ls1088ardb: Add serdes bindings
.../bindings/net/dsa/renesas,rzn1-a5psw.yaml | 1 +
.../bindings/net/ethernet-controller.yaml | 10 +-
.../bindings/net/fsl,fman-dtsec.yaml | 172 +++
.../bindings/net/fsl,qoriq-mc-dpmac.yaml | 2 +-
.../devicetree/bindings/net/fsl-fman.txt | 133 +-
.../devicetree/bindings/phy/fsl,lynx-10g.yaml | 311 ++++
Documentation/driver-api/phy/index.rst | 1 +
Documentation/driver-api/phy/lynx_10g.rst | 73 +
MAINTAINERS | 6 +
.../boot/dts/freescale/fsl-ls1043-post.dtsi | 24 +
.../boot/dts/freescale/fsl-ls1046-post.dtsi | 25 +
.../boot/dts/freescale/fsl-ls1046a-rdb.dts | 34 +
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 179 +++
.../boot/dts/freescale/fsl-ls1088a-rdb.dts | 87 ++
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 96 ++
.../fsl/qoriq-fman3-0-10g-0-best-effort.dtsi | 3 +-
.../boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi | 10 +-
.../fsl/qoriq-fman3-0-10g-1-best-effort.dtsi | 10 +-
.../boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi | 10 +-
.../boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi | 3 +-
.../boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi | 10 +-
.../boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi | 10 +-
.../boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi | 10 +-
.../boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi | 3 +-
.../boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi | 10 +-
.../boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi | 10 +-
.../boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi | 10 +-
.../boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi | 3 +-
.../boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi | 10 +-
.../boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi | 10 +-
.../boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi | 10 +-
.../boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi | 3 +-
.../boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi | 10 +-
drivers/net/ethernet/freescale/dpaa/Kconfig | 4 +-
.../net/ethernet/freescale/dpaa/dpaa_eth.c | 132 +-
.../ethernet/freescale/dpaa/dpaa_eth_sysfs.c | 2 +-
.../ethernet/freescale/dpaa/dpaa_ethtool.c | 90 +-
drivers/net/ethernet/freescale/fman/Kconfig | 4 +-
drivers/net/ethernet/freescale/fman/fman.c | 31 +-
drivers/net/ethernet/freescale/fman/fman.h | 31 +-
.../net/ethernet/freescale/fman/fman_dtsec.c | 674 ++++-----
.../net/ethernet/freescale/fman/fman_dtsec.h | 58 +-
.../net/ethernet/freescale/fman/fman_keygen.c | 29 +-
.../net/ethernet/freescale/fman/fman_keygen.h | 29 +-
.../net/ethernet/freescale/fman/fman_mac.h | 34 +-
.../net/ethernet/freescale/fman/fman_memac.c | 864 +++++------
.../net/ethernet/freescale/fman/fman_memac.h | 57 +-
.../net/ethernet/freescale/fman/fman_muram.c | 31 +-
.../net/ethernet/freescale/fman/fman_muram.h | 32 +-
.../net/ethernet/freescale/fman/fman_port.c | 29 +-
.../net/ethernet/freescale/fman/fman_port.h | 29 +-
drivers/net/ethernet/freescale/fman/fman_sp.c | 29 +-
drivers/net/ethernet/freescale/fman/fman_sp.h | 28 +-
.../net/ethernet/freescale/fman/fman_tgec.c | 274 ++--
.../net/ethernet/freescale/fman/fman_tgec.h | 54 +-
drivers/net/ethernet/freescale/fman/mac.c | 653 +--------
drivers/net/ethernet/freescale/fman/mac.h | 66 +-
drivers/net/phy/aquantia_main.c | 86 +-
drivers/net/phy/phy.c | 21 +
drivers/net/phy/phylink.c | 161 +-
drivers/phy/freescale/Kconfig | 20 +
drivers/phy/freescale/Makefile | 3 +
drivers/phy/freescale/lynx-10g.h | 36 +
drivers/phy/freescale/phy-fsl-lynx-10g-clk.c | 438 ++++++
drivers/phy/freescale/phy-fsl-lynx-10g.c | 1297 +++++++++++++++++
drivers/soc/fsl/qbman/qman.c | 76 +-
include/linux/phy.h | 42 +
include/linux/phylink.h | 12 +-
include/soc/fsl/qman.h | 9 +
69 files changed, 4408 insertions(+), 2356 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
create mode 100644 Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
create mode 100644 Documentation/driver-api/phy/lynx_10g.rst
create mode 100644 drivers/phy/freescale/lynx-10g.h
create mode 100644 drivers/phy/freescale/phy-fsl-lynx-10g-clk.c
create mode 100644 drivers/phy/freescale/phy-fsl-lynx-10g.c
--
2.35.1.1320.gc452695387.dirty
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH net-next v3 01/47] dt-bindings: phy: Add Lynx 10G phy binding
2022-07-15 21:59 [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink Sean Anderson
@ 2022-07-15 21:59 ` Sean Anderson
2022-07-20 22:17 ` Rob Herring
2022-07-15 21:59 ` [PATCH net-next v3 03/47] dt-bindings: net: Convert FMan MAC bindings to yaml Sean Anderson
` (9 subsequent siblings)
10 siblings, 1 reply; 30+ messages in thread
From: Sean Anderson @ 2022-07-15 21:59 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Madalin Bucur, netdev
Cc: Paolo Abeni, Eric Dumazet, linux-arm-kernel, Russell King,
linux-kernel, Sean Anderson, Kishon Vijay Abraham I,
Krzysztof Kozlowski, Rob Herring, Vinod Koul, devicetree,
linux-phy
This adds a binding for the SerDes module found on QorIQ processors. The
phy reference has two cells, one for the first lane and one for the
last. This should allow for good support of multi-lane protocols when
(if) they are added. There is no protocol option, because the driver is
designed to be able to completely reconfigure lanes at runtime.
Generally, the phy consumer can select the appropriate protocol using
set_mode. For the most part there is only one protocol controller
(consumer) per lane/protocol combination. The exception to this is the
B4860 processor, which has some lanes which can be connected to
multiple MACs. For that processor, I anticipate the easiest way to
resolve this will be to add an additional cell with a "protocol
controller instance" property.
Each serdes has a unique set of supported protocols (and lanes). The
support matrix is configured in the device tree. The format of each
PCCR (protocol configuration register) is modeled. Although the general
format is typically the same across different SoCs, the specific
supported protocols (and the values necessary to select them) are
particular to individual SerDes. A nested structure is used to reduce
duplication of data.
There are two PLLs, each of which can be used as the master clock for
each lane. Each PLL has its own reference. For the moment they are
required, because it simplifies the driver implementation. Absent
reference clocks can be modeled by a fixed-clock with a rate of 0.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---
Changes in v3:
- Manually expand yaml references
- Add mode configuration to device tree
Changes in v2:
- Rename to fsl,lynx-10g.yaml
- Refer to the device in the documentation, rather than the binding
- Move compatible first
- Document phy cells in the description
- Allow a value of 1 for phy-cells. This allows for compatibility with
the similar (but according to Ioana Ciornei different enough) lynx-28g
binding.
- Remove minItems
- Use list for clock-names
- Fix example binding having too many cells in regs
- Add #clock-cells. This will allow using assigned-clocks* to configure
the PLLs.
- Document the structure of the compatible strings
.../devicetree/bindings/phy/fsl,lynx-10g.yaml | 311 ++++++++++++++++++
1 file changed, 311 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
new file mode 100644
index 000000000000..a2c37225bb67
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
@@ -0,0 +1,311 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/fsl,lynx-10g.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP Lynx 10G SerDes
+
+maintainers:
+ - Sean Anderson <sean.anderson@seco.com>
+
+description: |
+ These Lynx "SerDes" devices are found in NXP's QorIQ line of processors. The
+ SerDes provides up to eight lanes. Each lane may be configured individually,
+ or may be combined with adjacent lanes for a multi-lane protocol. The SerDes
+ supports a variety of protocols, including up to 10G Ethernet, PCIe, SATA, and
+ others. The specific protocols supported for each lane depend on the
+ particular SoC.
+
+definitions:
+ fsl,cfg:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ description: |
+ The configuration value to program into the field.
+
+ fsl,first-lane:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 7
+ description: |
+ The first lane in the group configured by fsl,cfg. This lane will have
+ the FIRST_LANE bit set in GCR0. The reset direction will also be set
+ based on whether this property is less than or greater than
+ fsl,last-lane.
+
+ fsl,last-lane:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 7
+ description: |
+ The last lane configured by fsl,cfg. If this property is absent,
+ then it will default to the value of fsl,first-lane.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - fsl,ls1046a-serdes
+ - fsl,ls1088a-serdes
+ - const: fsl,lynx-10g
+
+ "#clock-cells":
+ const: 1
+ description: |
+ The cell contains the index of the PLL, starting from 0. Note that when
+ assigning a rate to a PLL, the PLLs' rates are divided by 1000 to avoid
+ overflow. A rate of 5000000 corresponds to 5GHz.
+
+ "#phy-cells":
+ minimum: 1
+ maximum: 2
+ description: |
+ The cells contain the following arguments:
+ - The first lane in the group. Lanes are numbered based on the register
+ offsets, not the I/O ports. This corresponds to the letter-based ("Lane
+ A") naming scheme, and not the number-based ("Lane 0") naming scheme. On
+ most SoCs, "Lane A" is "Lane 0", but not always.
+ - Last lane. For single-lane protocols, this should be the same as the
+ first lane.
+ If no lanes in a SerDes can be grouped, then #phy-cells may be 1, and the
+ first cell will specify the only lane in the group.
+
+ clocks:
+ maxItems: 2
+ description: |
+ Clock for each PLL reference clock input.
+
+ clock-names:
+ minItems: 2
+ maxItems: 2
+ items:
+ enum:
+ - ref0
+ - ref1
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ '^pccr-':
+ type: object
+
+ description: |
+ One of the protocol configuration registers (PCCRs). These contains
+ several fields, each of which mux a particular protocol onto a particular
+ lane.
+
+ properties:
+ fsl,pccr:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ The index of the PCCR. This is the same as the register name suffix.
+ For example, a node for PCCRB would use a value of '0xb' for an
+ offset of 0x22C (0x200 + 4 * 0xb).
+
+ patternProperties:
+ '^(q?sgmii|xfi|pcie|sata)-':
+ type: object
+
+ description: |
+ A configuration field within a PCCR. Each field configures one
+ protocol controller. The value of the field determines the lanes the
+ controller is connected to, if any.
+
+ properties:
+ fsl,index:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ The index of the field. This corresponds to the suffix in the
+ documentation. For example, PEXa would be 0, PEXb 1, etc.
+ Generally, higher fields occupy lower bits.
+
+ If there are any subnodes present, they will be preferred over
+ fsl,cfg et. al.
+
+ fsl,cfg:
+ $ref: "#/definitions/fsl,cfg"
+
+ fsl,first-lane:
+ $ref: "#/definitions/fsl,first-lane"
+
+ fsl,last-lane:
+ $ref: "#/definitions/fsl,last-lane"
+
+ fsl,proto:
+ $ref: /schemas/types.yaml#/definitions/string
+ enum:
+ - sgmii
+ - sgmii25
+ - qsgmii
+ - xfi
+ - pcie
+ - sata
+ description: |
+ Indicates the basic group protocols supported by this field.
+ Individual protocols are selected by configuring the protocol
+ controller.
+
+ - sgmii: 1000BASE-X, SGMII, and 1000BASE-KX (depending on the
+ SoC)
+ - sgmii25: 2500BASE-X, 1000BASE-X, SGMII, and 1000BASE-KX
+ (depending on the SoC)
+ - qsgmii: QSGMII
+ - xfi: 10GBASE-R and 10GBASE-KR (depending on the SoC)
+ - pcie: PCIe
+ - sata: SATA
+
+ patternProperties:
+ '^cfg-':
+ type: object
+
+ description: |
+ A single field may have multiple values which, when programmed,
+ connect the protocol controller to different lanes. If this is the
+ case, multiple sub-nodes may be provided, each describing a
+ single muxing.
+
+ properties:
+ fsl,cfg:
+ $ref: "#/definitions/fsl,cfg"
+
+ fsl,first-lane:
+ $ref: "#/definitions/fsl,first-lane"
+
+ fsl,last-lane:
+ $ref: "#/definitions/fsl,last-lane"
+
+ required:
+ - fsl,cfg
+ - fsl,first-lane
+
+ dependencies:
+ fsl,last-lane:
+ - fsl,first-lane
+
+ additionalProperties: false
+
+ required:
+ - fsl,index
+ - fsl,proto
+
+ dependencies:
+ fsl,last-lane:
+ - fsl,first-lane
+ fsl,cfg:
+ - fsl,first-lane
+ fsl,first-lane:
+ - fsl,cfg
+
+ # I would like to require either a config subnode or the config
+ # properties (and not both), but from what I can tell that can't be
+ # expressed in json schema. In particular, it is not possible to
+ # require a pattern property.
+
+ additionalProperties: false
+
+ required:
+ - fsl,pccr
+
+ additionalProperties: false
+
+required:
+ - "#clock-cells"
+ - "#phy-cells"
+ - compatible
+ - clocks
+ - clock-names
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ serdes1: phy@1ea0000 {
+ #clock-cells = <1>;
+ #phy-cells = <2>;
+ compatible = "fsl,ls1088a-serdes", "fsl,lynx-10g";
+ reg = <0x1ea0000 0x2000>;
+ clocks = <&clk_100mhz>, <&clk_156_mhz>;
+ clock-names = "ref0", "ref1";
+ assigned-clocks = <&serdes1 0>;
+ assigned-clock-rates = <5000000>;
+
+ pccr-8 {
+ fsl,pccr = <0x8>;
+
+ sgmii-0 {
+ fsl,index = <0>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <3>;
+ fsl,proto = "sgmii";
+ };
+
+ sgmii-1 {
+ fsl,index = <1>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <2>;
+ fsl,proto = "sgmii";
+ };
+
+ sgmii-2 {
+ fsl,index = <2>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <1>;
+ fsl,proto = "sgmii25";
+ };
+
+ sgmii-3 {
+ fsl,index = <3>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <0>;
+ fsl,proto = "sgmii25";
+ };
+ };
+
+ pccr-9 {
+ fsl,pccr = <0x9>;
+
+ qsgmii-0 {
+ fsl,index = <0>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <3>;
+ fsl,proto = "qsgmii";
+ };
+
+ qsgmii-1 {
+ fsl,index = <1>;
+ fsl,proto = "qsgmii";
+
+ cfg-1 {
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <2>;
+ };
+
+ cfg-2 {
+ fsl,cfg = <0x2>;
+ fsl,first-lane = <0>;
+ };
+ };
+ };
+
+ pccr-b {
+ fsl,pccr = <0xb>;
+
+ xfi-0 {
+ fsl,index = <0>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <1>;
+ fsl,proto = "xfi";
+ };
+
+ xfi-1 {
+ fsl,index = <1>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <0>;
+ fsl,proto = "xfi";
+ };
+ };
+ };
+...
--
2.35.1.1320.gc452695387.dirty
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH net-next v3 03/47] dt-bindings: net: Convert FMan MAC bindings to yaml
2022-07-15 21:59 [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink Sean Anderson
2022-07-15 21:59 ` [PATCH net-next v3 01/47] dt-bindings: phy: Add Lynx 10G phy binding Sean Anderson
@ 2022-07-15 21:59 ` Sean Anderson
2022-07-15 23:06 ` Rob Herring
2022-07-15 21:59 ` [PATCH net-next v3 04/47] dt-bindings: net: fman: Add additional interface properties Sean Anderson
` (8 subsequent siblings)
10 siblings, 1 reply; 30+ messages in thread
From: Sean Anderson @ 2022-07-15 21:59 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Madalin Bucur, netdev
Cc: Paolo Abeni, Eric Dumazet, linux-arm-kernel, Russell King,
linux-kernel, Sean Anderson, Rob Herring, Krzysztof Kozlowski,
Rob Herring, devicetree
This converts the MAC portion of the FMan MAC bindings to yaml.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes in v3:
- Incorperate some minor changes into the first FMan binding commit
Changes in v2:
- New
.../bindings/net/fsl,fman-dtsec.yaml | 145 ++++++++++++++++++
.../devicetree/bindings/net/fsl-fman.txt | 128 +---------------
2 files changed, 146 insertions(+), 127 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
diff --git a/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
new file mode 100644
index 000000000000..78579ef839bf
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
@@ -0,0 +1,145 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP FMan MAC
+
+maintainers:
+ - Madalin Bucur <madalin.bucur@nxp.com>
+
+description: |
+ Each FMan has several MACs, each implementing an Ethernet interface. Earlier
+ versions of FMan used the Datapath Three Speed Ethernet Controller (dTSEC) for
+ 10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller
+ (10GEC) for 10 Gbit/s speeds. Later versions of FMan use the Multirate
+ Ethernet Media Access Controller (mEMAC) to handle all speeds.
+
+properties:
+ compatible:
+ enum:
+ - fsl,fman-dtsec
+ - fsl,fman-xgec
+ - fsl,fman-memac
+
+ cell-index:
+ maximum: 64
+ description: |
+ FManV2:
+ register[bit] MAC cell-index
+ ============================================================
+ FM_EPI[16] XGEC 8
+ FM_EPI[16+n] dTSECn n-1
+ FM_NPI[11+n] dTSECn n-1
+ n = 1,..,5
+
+ FManV3:
+ register[bit] MAC cell-index
+ ============================================================
+ FM_EPI[16+n] mEMACn n-1
+ FM_EPI[25] mEMAC10 9
+
+ FM_NPI[11+n] mEMACn n-1
+ FM_NPI[10] mEMAC10 9
+ FM_NPI[11] mEMAC9 8
+ n = 1,..8
+
+ FM_EPI and FM_NPI are located in the FMan memory map.
+
+ 2. SoC registers:
+
+ - P2041, P3041, P4080 P5020, P5040:
+ register[bit] FMan MAC cell
+ Unit index
+ ============================================================
+ DCFG_DEVDISR2[7] 1 XGEC 8
+ DCFG_DEVDISR2[7+n] 1 dTSECn n-1
+ DCFG_DEVDISR2[15] 2 XGEC 8
+ DCFG_DEVDISR2[15+n] 2 dTSECn n-1
+ n = 1,..5
+
+ - T1040, T2080, T4240, B4860:
+ register[bit] FMan MAC cell
+ Unit index
+ ============================================================
+ DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1
+ DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1
+ n = 1,..6,9,10
+
+ EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
+ the specific SoC "Device Configuration/Pin Control" Memory
+ Map.
+
+ reg:
+ maxItems: 1
+
+ fsl,fman-ports:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 2
+ description: |
+ An array of two references: the first is the FMan RX port and the second
+ is the TX port used by this MAC.
+
+ ptp-timer:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: A reference to the IEEE1588 timer
+
+ pcsphy-handle:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: A reference to the PCS (typically found on the SerDes)
+
+ tbi-handle:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: A reference to the (TBI-based) PCS
+
+required:
+ - compatible
+ - cell-index
+ - reg
+ - fsl,fman-ports
+ - ptp-timer
+
+allOf:
+ - $ref: ethernet-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,fman-dtsec
+ then:
+ required:
+ - tbi-handle
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,fman-memac
+ then:
+ required:
+ - pcsphy-handle
+
+additionalProperties: false
+
+examples:
+ - |
+ ethernet@e0000 {
+ compatible = "fsl,fman-dtsec";
+ cell-index = <0>;
+ reg = <0xe0000 0x1000>;
+ fsl,fman-ports = <&fman1_rx8 &fman1_tx28>;
+ ptp-timer = <&ptp_timer>;
+ tbi-handle = <&tbi0>;
+ };
+ - |
+ ethernet@e8000 {
+ cell-index = <4>;
+ compatible = "fsl,fman-memac";
+ reg = <0xe8000 0x1000>;
+ fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
+ ptp-timer = <&ptp_timer0>;
+ pcsphy-handle = <&pcsphy4>;
+ phy-handle = <&sgmii_phy1>;
+ phy-connection-type = "sgmii";
+ };
+...
diff --git a/Documentation/devicetree/bindings/net/fsl-fman.txt b/Documentation/devicetree/bindings/net/fsl-fman.txt
index 801efc7d6818..b9055335db3b 100644
--- a/Documentation/devicetree/bindings/net/fsl-fman.txt
+++ b/Documentation/devicetree/bindings/net/fsl-fman.txt
@@ -232,133 +232,7 @@ port@81000 {
=============================================================================
FMan dTSEC/XGEC/mEMAC Node
-DESCRIPTION
-
-mEMAC/dTSEC/XGEC are the Ethernet network interfaces
-
-PROPERTIES
-
-- compatible
- Usage: required
- Value type: <stringlist>
- Definition: A standard property.
- Must include one of the following:
- - "fsl,fman-dtsec" for dTSEC MAC
- - "fsl,fman-xgec" for XGEC MAC
- - "fsl,fman-memac" for mEMAC MAC
-
-- cell-index
- Usage: required
- Value type: <u32>
- Definition: Specifies the MAC id.
-
- The cell-index value may be used by the FMan or the SoC, to
- identify the MAC unit in the FMan (or SoC) memory map.
- In the tables below there's a description of the cell-index
- use, there are two tables, one describes the use of cell-index
- by the FMan, the second describes the use by the SoC:
-
- 1. FMan Registers
-
- FManV2:
- register[bit] MAC cell-index
- ============================================================
- FM_EPI[16] XGEC 8
- FM_EPI[16+n] dTSECn n-1
- FM_NPI[11+n] dTSECn n-1
- n = 1,..,5
-
- FManV3:
- register[bit] MAC cell-index
- ============================================================
- FM_EPI[16+n] mEMACn n-1
- FM_EPI[25] mEMAC10 9
-
- FM_NPI[11+n] mEMACn n-1
- FM_NPI[10] mEMAC10 9
- FM_NPI[11] mEMAC9 8
- n = 1,..8
-
- FM_EPI and FM_NPI are located in the FMan memory map.
-
- 2. SoC registers:
-
- - P2041, P3041, P4080 P5020, P5040:
- register[bit] FMan MAC cell
- Unit index
- ============================================================
- DCFG_DEVDISR2[7] 1 XGEC 8
- DCFG_DEVDISR2[7+n] 1 dTSECn n-1
- DCFG_DEVDISR2[15] 2 XGEC 8
- DCFG_DEVDISR2[15+n] 2 dTSECn n-1
- n = 1,..5
-
- - T1040, T2080, T4240, B4860:
- register[bit] FMan MAC cell
- Unit index
- ============================================================
- DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1
- DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1
- n = 1,..6,9,10
-
- EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
- the specific SoC "Device Configuration/Pin Control" Memory
- Map.
-
-- reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property.
-
-- fsl,fman-ports
- Usage: required
- Value type: <prop-encoded-array>
- Definition: An array of two phandles - the first references is
- the FMan RX port and the second is the TX port used by this
- MAC.
-
-- ptp-timer
- Usage required
- Value type: <phandle>
- Definition: A phandle for 1EEE1588 timer.
-
-- pcsphy-handle
- Usage required for "fsl,fman-memac" MACs
- Value type: <phandle>
- Definition: A phandle for pcsphy.
-
-- tbi-handle
- Usage required for "fsl,fman-dtsec" MACs
- Value type: <phandle>
- Definition: A phandle for tbiphy.
-
-EXAMPLE
-
-fman1_tx28: port@a8000 {
- cell-index = <0x28>;
- compatible = "fsl,fman-v2-port-tx";
- reg = <0xa8000 0x1000>;
-};
-
-fman1_rx8: port@88000 {
- cell-index = <0x8>;
- compatible = "fsl,fman-v2-port-rx";
- reg = <0x88000 0x1000>;
-};
-
-ptp-timer: ptp_timer@fe000 {
- compatible = "fsl,fman-ptp-timer";
- reg = <0xfe000 0x1000>;
-};
-
-ethernet@e0000 {
- compatible = "fsl,fman-dtsec";
- cell-index = <0>;
- reg = <0xe0000 0x1000>;
- fsl,fman-ports = <&fman1_rx8 &fman1_tx28>;
- ptp-timer = <&ptp-timer>;
- tbi-handle = <&tbi0>;
-};
+Refer to Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
============================================================================
FMan IEEE 1588 Node
--
2.35.1.1320.gc452695387.dirty
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH net-next v3 04/47] dt-bindings: net: fman: Add additional interface properties
2022-07-15 21:59 [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink Sean Anderson
2022-07-15 21:59 ` [PATCH net-next v3 01/47] dt-bindings: phy: Add Lynx 10G phy binding Sean Anderson
2022-07-15 21:59 ` [PATCH net-next v3 03/47] dt-bindings: net: Convert FMan MAC bindings to yaml Sean Anderson
@ 2022-07-15 21:59 ` Sean Anderson
2022-07-15 21:59 ` [PATCH net-next v3 06/47] [RFT] phy: fsl: Add Lynx 10G SerDes driver Sean Anderson
` (7 subsequent siblings)
10 siblings, 0 replies; 30+ messages in thread
From: Sean Anderson @ 2022-07-15 21:59 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Madalin Bucur, netdev
Cc: Paolo Abeni, Eric Dumazet, linux-arm-kernel, Russell King,
linux-kernel, Sean Anderson, Krzysztof Kozlowski, Rob Herring,
devicetree
At the moment, mEMACs are configured almost completely based on the
phy-connection-type. That is, if the phy interface is RGMII, it assumed
that RGMII is supported. For some interfaces, it is assumed that the
RCW/bootloader has set up the SerDes properly. This is generally OK, but
restricts runtime reconfiguration. The actual link state is never
reported.
To address these shortcomings, the driver will need additional
information. First, it needs to know how to access the PCS/PMAs (in
order to configure them and get the link status). The SGMII PCS/PMA is
the only currently-described PCS/PMA. Add the XFI and QSGMII PCS/PMAs as
well. The XFI (and 10GBASE-KR) PCS/PMA is a c45 "phy" which sits on the
same MDIO bus as SGMII PCS/PMA. By default they will have conflicting
addresses, but they are also not enabled at the same time by default.
Therefore, we can let the XFI PCS/PMA be the default when
phy-connection-type is xgmii. This will allow for
backwards-compatibility.
QSGMII, however, cannot work with the current binding. This is because
the QSGMII PCS/PMAs are only present on one MAC's MDIO bus. At the
moment this is worked around by having every MAC write to the PCS/PMA
addresses (without checking if they are present). This only works if
each MAC has the same configuration, and only if we don't need to know
the status. Because the QSGMII PCS/PMA will typically be located on a
different MDIO bus than the MAC's SGMII PCS/PMA, there is no fallback
for the QSGMII PCS/PMA.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---
Changes in v3:
- Add vendor prefix 'fsl,' to rgmii and mii properties.
- Set maxItems for pcs-names
- Remove phy-* properties from example because dt-schema complains and I
can't be bothered to figure out how to make it work.
- Add pcs-handle as a preferred version of pcsphy-handle
- Deprecate pcsphy-handle
- Remove mii/rmii properties
Changes in v2:
- Better document how we select which PCS to use in the default case
.../bindings/net/fsl,fman-dtsec.yaml | 53 ++++++++++++++-----
.../devicetree/bindings/net/fsl-fman.txt | 5 +-
2 files changed, 43 insertions(+), 15 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
index 78579ef839bf..4abf2f93667e 100644
--- a/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
+++ b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
@@ -85,9 +85,39 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle
description: A reference to the IEEE1588 timer
+ phys:
+ description: A reference to the SerDes lane(s)
+ maxItems: 1
+
+ phy-names:
+ items:
+ - const: serdes
+
pcsphy-handle:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: A reference to the PCS (typically found on the SerDes)
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ minItems: 1
+ maxItems: 3
+ deprecated: true
+ description: See pcs-handle.
+
+ pcs-handle:
+ minItems: 1
+ maxItems: 3
+ description: |
+ A reference to the various PCSs (typically found on the SerDes). If
+ pcs-names is absent, and phy-connection-type is "xgmii", then the first
+ reference will be assumed to be for "xfi". Otherwise, if pcs-names is
+ absent, then the first reference will be assumed to be for "sgmii".
+
+ pcs-names:
+ minItems: 1
+ maxItems: 3
+ items:
+ enum:
+ - sgmii
+ - qsgmii
+ - xfi
+ description: The type of each PCS in pcsphy-handle.
tbi-handle:
$ref: /schemas/types.yaml#/definitions/phandle
@@ -100,6 +130,10 @@ required:
- fsl,fman-ports
- ptp-timer
+dependencies:
+ pcs-names:
+ - pcs-handle
+
allOf:
- $ref: ethernet-controller.yaml#
- if:
@@ -110,14 +144,6 @@ allOf:
then:
required:
- tbi-handle
- - if:
- properties:
- compatible:
- contains:
- const: fsl,fman-memac
- then:
- required:
- - pcsphy-handle
additionalProperties: false
@@ -138,8 +164,9 @@ examples:
reg = <0xe8000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
ptp-timer = <&ptp_timer0>;
- pcsphy-handle = <&pcsphy4>;
- phy-handle = <&sgmii_phy1>;
- phy-connection-type = "sgmii";
+ pcs-handle = <&pcsphy4>, <&qsgmiib_pcs1>;
+ pcs-names = "sgmii", "qsgmii";
+ phys = <&serdes1 1>;
+ phy-names = "serdes";
};
...
diff --git a/Documentation/devicetree/bindings/net/fsl-fman.txt b/Documentation/devicetree/bindings/net/fsl-fman.txt
index b9055335db3b..bda4b41af074 100644
--- a/Documentation/devicetree/bindings/net/fsl-fman.txt
+++ b/Documentation/devicetree/bindings/net/fsl-fman.txt
@@ -320,8 +320,9 @@ For internal PHY device on internal mdio bus, a PHY node should be created.
See the definition of the PHY node in booting-without-of.txt for an
example of how to define a PHY (Internal PHY has no interrupt line).
- For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.
-- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY,
- PCS PHY addr must be '0'.
+- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY.
+ The PCS PHY address should correspond to the value of the appropriate
+ MDEV_PORT.
EXAMPLE
--
2.35.1.1320.gc452695387.dirty
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH net-next v3 06/47] [RFT] phy: fsl: Add Lynx 10G SerDes driver
2022-07-15 21:59 [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink Sean Anderson
` (2 preceding siblings ...)
2022-07-15 21:59 ` [PATCH net-next v3 04/47] dt-bindings: net: fman: Add additional interface properties Sean Anderson
@ 2022-07-15 21:59 ` Sean Anderson
2022-07-16 22:39 ` kernel test robot
2022-07-15 21:59 ` [PATCH net-next v3 42/47] powerpc: dts: qoriq: Add nodes for QSGMII PCSs Sean Anderson
` (6 subsequent siblings)
10 siblings, 1 reply; 30+ messages in thread
From: Sean Anderson @ 2022-07-15 21:59 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Madalin Bucur, netdev
Cc: Paolo Abeni, Eric Dumazet, linux-arm-kernel, Russell King,
linux-kernel, Sean Anderson, Ioana Ciornei, Jonathan Corbet,
Kishon Vijay Abraham I, Krzysztof Kozlowski, Rob Herring,
Vinod Koul, devicetree, linux-doc, linux-phy
This adds support for the Lynx 10G "SerDes" devices found on various NXP
QorIQ SoCs. There may be up to four SerDes devices on each SoC, each
supporting up to eight lanes. Protocol support for each SerDes is highly
heterogeneous, with each SoC typically having a totally different
selection of supported protocols for each lane. Additionally, the SerDes
devices on each SoC also have differing support. One SerDes will
typically support Ethernet on most lanes, while the other will typically
support PCIe on most lanes.
There is wide hardware support for this SerDes. I have not done
extensive digging, but it seems to be used on almost every QorIQ device,
including the AMP and Layerscape series. Because each SoC typically has
specific instructions and exceptions for its SerDes, I have limited the
initial scope of this module to just the LS1046A and LS1088A.
Additionally, I have only added support for Ethernet protocols. There is
not a great need for dynamic reconfiguration for other protocols (SATA
and PCIe handle rate changes in hardware), so support for them may never
be added.
Nevertheless, I have tried to provide an obvious path for adding support
for other SoCs as well as other protocols. SATA just needs support for
configuring LNmSSCR0. PCIe may need to configure the equalization
registers. It also uses multiple lanes. I have tried to write the driver
with multi-lane support in mind, so there should not need to be any large
changes. Although there are 6 protocols supported, I have only tested SGMII
and XFI. The rest have been implemented as described in the datasheet.
Most of these protocols should work "as-is", but 10GBASE-KR will need
PCS support for link training.
The PLLs are modeled as clocks proper. This lets us take advantage of the
existing clock infrastructure. I have not given the same treatment to the
lane "clocks" (dividers) because they need to be programmed in-concert with
the rest of the lane settings. One tricky thing is that the VCO (pll) rate
exceeds 2^32 (maxing out at around 5GHz). This will be a problem on 32-bit
platforms, since clock rates are stored as unsigned longs. To work around
this, the pll clock rate is generally treated in units of kHz.
The PLLs are configured rather interestingly. Instead of the usual direct
programming of the appropriate divisors, the input and output clock rates
are selected directly. Generally, the only restriction is that the input
and output must be integer multiples of each other. This suggests some kind
of internal look-up table. The datasheets generally list out the supported
combinations explicitly, and not all input/output combinations are
documented. I'm not sure if this is due to lack of support, or due to an
oversight. If this becomes an issue, then some combinations can be
blacklisted (or whitelisted). This may also be necessary for other SoCs
which have more stringent clock requirements.
The general API call list for this PHY is documented under the driver-api
docs. I think this is rather standard, except that most drivers configure
the mode (protocol) at xlate-time. Unlike some other phys where e.g. PCIe
x4 will use 4 separate phys all configured for PCIe, this driver uses one
phy configured to use 4 lanes. This is because while the individual lanes
may be configured individually, the protocol selection acts on all lanes at
once. Additionally, the order which lanes should be configured in is
specified by the datasheet. To coordinate this, lanes are reserved in
phy_init, and released in phy_exit.
When getting a phy (backed by struct lynx_group), if a phy already
exists for those lanes, it is reused. This is to make things like
QSGMII work. Four MACs will all want to ensure that the lane is
configured properly, and we need to ensure they can all call phy_init,
etc. There is refcounting for phy_init and phy_power_on, so the phy will
only be powered on once. However, there is no refcounting for
phy_set_mode. A "rogue" MAC could set the mode to something non-QSGMII
and break the other MACs. Perhaps there is an opportunity for future
enhancement here.
This driver was written with reference to the LS1046A reference manual.
However, it was informed by reference manuals for all processors with
mEMACs, especially the T4240 (which appears to have a "maxed-out"
configuration). The earlier PXXX processors appear to be similar, but
have a different overall register layout (using "banks" instead of
separate SerDes).
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---
XFI does not work when not selected in the RCW. This will not break any
existing boards (since they all select it if they use it).
Changes in v3:
- Rename remaining references to QorIQ SerDes to Lynx 10G
- Fix PLL enable sequence by waiting for our reset request to be cleared
before continuing. Do the same for the lock, even though it isn't as
critical. Because we will delay for 1.5ms on average, use prepare
instead of enable so we can sleep.
- Document the status of each protocol
- Fix offset of several bitfields in RECR0
- Take into account PLLRST_B, SDRST_B, and SDEN when considering whether
a PLL is "enabled."
- Only power off unused lanes.
- Split mode lane mask into first/last lane (like group)
- Read modes from device tree
- Use caps to determine whether KX/KR are supported
- Move modes to lynx_priv
- Ensure that the protocol controller is not already in-use when we try
to configure a new mode. This should only occur if the device tree is
misconfigured (e.g. when QSGMII is selected on two lanes but there is
only one QSGMII controller).
- Split PLL drivers off into their own file
- Add clock for "ext_dly" instead of writing the bit directly (and
racing with any clock code).
- Use kasprintf instead of open-coding the snprintf dance
- Support 1000BASE-KX in lynx_lookup_proto. This still requires PCS
support, so nothing is truly "enabled" yet.
Changes in v2:
- Rename driver to Lynx 10G (etc.)
- Fix not clearing group->pll after disabling it
- Support 1 and 2 phy-cells
- Power off lanes during probe
- Clear SGMIIaCR1_PCS_EN during probe
- Rename LYNX_PROTO_UNKNOWN to LYNX_PROTO_NONE
- Handle 1000BASE-KX in lynx_proto_mode_prep
Documentation/driver-api/phy/index.rst | 1 +
Documentation/driver-api/phy/lynx_10g.rst | 73 +
MAINTAINERS | 6 +
drivers/phy/freescale/Kconfig | 19 +
drivers/phy/freescale/Makefile | 3 +
drivers/phy/freescale/lynx-10g.h | 36 +
drivers/phy/freescale/phy-fsl-lynx-10g-clk.c | 438 ++++++
drivers/phy/freescale/phy-fsl-lynx-10g.c | 1297 ++++++++++++++++++
8 files changed, 1873 insertions(+)
create mode 100644 Documentation/driver-api/phy/lynx_10g.rst
create mode 100644 drivers/phy/freescale/lynx-10g.h
create mode 100644 drivers/phy/freescale/phy-fsl-lynx-10g-clk.c
create mode 100644 drivers/phy/freescale/phy-fsl-lynx-10g.c
diff --git a/Documentation/driver-api/phy/index.rst b/Documentation/driver-api/phy/index.rst
index 69ba1216de72..c9b7a4698dab 100644
--- a/Documentation/driver-api/phy/index.rst
+++ b/Documentation/driver-api/phy/index.rst
@@ -7,6 +7,7 @@ Generic PHY Framework
.. toctree::
phy
+ lynx_10g
samsung-usb2
.. only:: subproject and html
diff --git a/Documentation/driver-api/phy/lynx_10g.rst b/Documentation/driver-api/phy/lynx_10g.rst
new file mode 100644
index 000000000000..aa445911d77d
--- /dev/null
+++ b/Documentation/driver-api/phy/lynx_10g.rst
@@ -0,0 +1,73 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+===========================
+Lynx 10G Phy (QorIQ SerDes)
+===========================
+
+Using this phy
+--------------
+
+The general order of calls should be::
+
+ [devm_][of_]phy_get()
+ phy_init()
+ phy_power_on()
+ phy_set_mode[_ext]()
+ ...
+ phy_power_off()
+ phy_exit()
+ [[of_]phy_put()]
+
+:c:func:`phy_get` just gets (or creates) a new :c:type:`phy` with the lanes
+described in the phandle. :c:func:`phy_init` is what actually reserves the
+lanes for use. Unlike some other drivers, when the phy is created, there is no
+default protocol. :c:func:`phy_set_mode <phy_set_mode_ext>` must be called in
+order to set the protocol.
+
+Supporting SoCs
+---------------
+
+Each new SoC needs a :c:type:`struct lynx_conf <lynx_conf>`, containing the
+number of lanes in each device, the endianness of the device, and a bitmask of
+capabilities ("caps"). For example, the configuration for the LS1046A is::
+
+ static const struct lynx_conf ls1046a_conf = {
+ .lanes = 4,
+ .caps = BIT(LYNX_HAS_1000BASEKX) | BIT(LYNX_HAS_10GKR),
+ .endian = REGMAP_ENDIAN_BIG,
+ };
+
+In addition, you will need to add a device node as documented in
+``Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml``. It is important
+that the list of modes is complete, even if not all protocols are supported.
+This lets the driver know which lanes are available, and which have been
+configured by the RCW.
+
+If a protocol is missing, add it to :c:type:`enum lynx_protocol
+<lynx_protocol>`, and to ``UNSUPPORTED_PROTOS``. If the PCCR shifts/masks for
+your protocol are missing, you will need to add them to
+:c:func:`lynx_proto_mode_mask` and :c:func:`lynx_proto_mode_shift`. Lastly, you
+will also need to add the mode to :c:func:`lynx_parse_pccrs`.
+
+Supporting Protocols
+--------------------
+
+Each protocol is a combination of values which must be programmed into the lane
+registers. To add a new protocol, first add it to :c:type:`enum lynx_protocol
+<lynx_protocol>`. If it is in ``UNSUPPORTED_PROTOS``, remove it. Add a new
+entry to `lynx_proto_params`, and populate the appropriate fields. You may need
+to add some new members to support new fields. Modify `lynx_lookup_proto` to
+map the :c:type:`enum phy_mode <phy_mode>` to :c:type:`enum lynx_protocol
+<lynx_protocol>`. Ensure that :c:func:`lynx_proto_mode_mask` and
+:c:func:`lynx_proto_mode_shift` have been updated with support for your
+protocol.
+
+You may need to modify :c:func:`lynx_set_mode` in order to support your
+protocol. This can happen when you have added members to :c:type:`struct
+lynx_proto_params <lynx_proto_params>`. It can also happen if you have specific
+clocking requirements, or protocol-specific registers to program.
+
+Internal API Reference
+----------------------
+
+.. kernel-doc:: drivers/phy/freescale/phy-fsl-lynx-10g.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 66738c8330db..085e110da079 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11799,6 +11799,12 @@ S: Maintained
W: http://linux-test-project.github.io/
T: git git://github.com/linux-test-project/ltp.git
+LYNX 10G SERDES DRIVER
+M: Sean Anderson <sean.anderson@seco.com>
+S: Maintained
+F: Documentation/driver-api/phy/lynx_10g.rst
+F: drivers/phy/freescale/phy-fsl-lynx-10g.c
+
LYNX 28G SERDES PHY DRIVER
M: Ioana Ciornei <ioana.ciornei@nxp.com>
L: netdev@vger.kernel.org
diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
index f9c54cd02036..fe2a3efe0ba4 100644
--- a/drivers/phy/freescale/Kconfig
+++ b/drivers/phy/freescale/Kconfig
@@ -38,3 +38,22 @@ config PHY_FSL_LYNX_28G
found on NXP's Layerscape platforms such as LX2160A.
Used to change the protocol running on SerDes lanes at runtime.
Only useful for a restricted set of Ethernet protocols.
+
+config PHY_FSL_LYNX_10G
+ tristate "Freescale Layerscale Lynx 10G SerDes support"
+ select GENERIC_PHY
+ select REGMAP_MMIO
+ help
+ This adds support for the Lynx "SerDes" devices found on various QorIQ
+ SoCs. There may be up to four SerDes devices on each SoC, and each
+ device supports up to eight lanes. The SerDes is configured by default
+ by the RCW, but this module is necessary in order to support dynamic
+ reconfiguration (such as to support 1G and 10G ethernet on the same
+ interface). The hardware supports a variety of protocols, including
+ Ethernet, SATA, PCIe, and more exotic links such as Interlaken and
+ Aurora. This driver only supports Ethernet, but it will try not to
+ touch lanes configured for other protocols.
+
+ If you have a QorIQ processor and want to dynamically reconfigure your
+ SerDes, say Y. If this driver is compiled as a module, it will be
+ named phy-fsl-lynx-10g-drv.
diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
index 3518d5dbe8a7..bd54ecef8b48 100644
--- a/drivers/phy/freescale/Makefile
+++ b/drivers/phy/freescale/Makefile
@@ -2,4 +2,7 @@
obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o
+phy-fsl-lynx-10g-drv-y += phy-fsl-lynx-10g.o
+phy-fsl-lynx-10g-drv-y += phy-fsl-lynx-10g-clk.o
+obj-$(CONFIG_PHY_FSL_LYNX_10G) += phy-fsl-lynx-10g-drv.o
obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o
diff --git a/drivers/phy/freescale/lynx-10g.h b/drivers/phy/freescale/lynx-10g.h
new file mode 100644
index 000000000000..882ab9da00bd
--- /dev/null
+++ b/drivers/phy/freescale/lynx-10g.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 Sean Anderson <sean.anderson@seco.com>
+ */
+
+#ifndef LYNX_10G
+#define LYNX_10G
+
+struct device;
+struct regmap;
+
+#include <linux/clk-provider.h>
+
+/**
+ * struct lynx_clk - Driver data for the PLLs
+ * @pll: The PLL clock
+ * @ex_dly: The "PLLa_ex_dly_clk" clock
+ * @ref: Our reference clock
+ * @dev: The serdes device
+ * @regmap: Our registers
+ * @idx: Which PLL this clock is for
+ */
+struct lynx_clk {
+ struct clk_hw pll, ex_dly;
+ struct clk *ref;
+ struct device *dev;
+ struct regmap *regmap;
+ unsigned int idx;
+};
+
+void lynx_pll_disable(struct clk_hw *hw);
+
+int lynx_clks_init(struct lynx_clk clks[2], struct device *dev,
+ struct regmap *regmap);
+
+#endif /* LYNX 10G */
diff --git a/drivers/phy/freescale/phy-fsl-lynx-10g-clk.c b/drivers/phy/freescale/phy-fsl-lynx-10g-clk.c
new file mode 100644
index 000000000000..dac5d2872a27
--- /dev/null
+++ b/drivers/phy/freescale/phy-fsl-lynx-10g-clk.c
@@ -0,0 +1,438 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Sean Anderson <sean.anderson@seco.com>
+ *
+ * This file contains the implementation for the PLLs found on Lynx 10G phys.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/math64.h>
+#include <linux/regmap.h>
+#include <linux/units.h>
+
+#include "lynx-10g.h"
+
+#define PLL_STRIDE 0x20
+#define PLLa(a, off) ((a) * PLL_STRIDE + (off))
+#define PLLaRSTCTL(a) PLLa(a, 0x00)
+#define PLLaCR0(a) PLLa(a, 0x04)
+
+#define PLLaRSTCTL_RSTREQ BIT(31)
+#define PLLaRSTCTL_RST_DONE BIT(30)
+#define PLLaRSTCTL_RST_ERR BIT(29)
+#define PLLaRSTCTL_PLLRST_B BIT(7)
+#define PLLaRSTCTL_SDRST_B BIT(6)
+#define PLLaRSTCTL_SDEN BIT(5)
+
+#define PLLaRSTCTL_ENABLE_SET (PLLaRSTCTL_RST_DONE | PLLaRSTCTL_PLLRST_B | \
+ PLLaRSTCTL_SDRST_B | PLLaRSTCTL_SDEN)
+#define PLLaRSTCTL_ENABLE_MASK (PLLaRSTCTL_ENABLE_SET | PLLaRSTCTL_RST_ERR)
+
+#define PLLaCR0_POFF BIT(31)
+#define PLLaCR0_RFCLK_SEL GENMASK(30, 28)
+#define PLLaCR0_PLL_LCK BIT(23)
+#define PLLaCR0_FRATE_SEL GENMASK(19, 16)
+#define PLLaCR0_DLYDIV_SEL GENMASK(1, 0)
+
+#define PLLaCR0_DLYDIV_SEL_16 0b01
+
+static u32 lynx_read(struct lynx_clk *clk, u32 reg)
+{
+ unsigned int ret = 0;
+
+ WARN_ON_ONCE(regmap_read(clk->regmap, reg, &ret));
+ return ret;
+}
+
+static void lynx_write(struct lynx_clk *clk, u32 val, u32 reg)
+{
+ WARN_ON_ONCE(regmap_write(clk->regmap, reg, val));
+}
+
+static struct lynx_clk *lynx_pll_to_clk(struct clk_hw *hw)
+{
+ return container_of(hw, struct lynx_clk, pll);
+}
+
+static struct lynx_clk *lynx_ex_dly_to_clk(struct clk_hw *hw)
+{
+ return container_of(hw, struct lynx_clk, ex_dly);
+}
+
+/* XXX: The output rate is in kHz to avoid overflow on 32-bit arches */
+
+void lynx_pll_disable(struct clk_hw *hw)
+{
+ struct lynx_clk *clk = lynx_pll_to_clk(hw);
+ u32 rstctl = lynx_read(clk, PLLaRSTCTL(clk->idx));
+
+ dev_dbg(clk->dev, "%s(pll%d)\n", __func__, clk->idx);
+
+ rstctl &= ~PLLaRSTCTL_SDRST_B;
+ lynx_write(clk, rstctl, PLLaRSTCTL(clk->idx));
+ ndelay(50);
+ rstctl &= ~(PLLaRSTCTL_SDEN | PLLaRSTCTL_PLLRST_B);
+ lynx_write(clk, rstctl, PLLaRSTCTL(clk->idx));
+ ndelay(100);
+}
+
+static int lynx_pll_prepare(struct clk_hw *hw)
+{
+ int ret;
+ struct lynx_clk *clk = lynx_pll_to_clk(hw);
+ u32 rstctl = lynx_read(clk, PLLaRSTCTL(clk->idx));
+
+ dev_dbg(clk->dev, "%s(pll%d) %.8x\n", __func__, clk->idx, rstctl);
+
+ /*
+ * "Enabling" the PLL involves resetting it (and all attached lanes).
+ * Avoid doing this if we are already enabled.
+ */
+ if (clk_hw_is_enabled(hw))
+ return 0;
+
+ rstctl |= PLLaRSTCTL_RSTREQ;
+ lynx_write(clk, rstctl, PLLaRSTCTL(clk->idx));
+ /* Wait for the reset request to clear */
+ ret = read_poll_timeout(lynx_read, rstctl,
+ !(rstctl & PLLaRSTCTL_RSTREQ), 10, 1000, true,
+ clk, PLLaRSTCTL(clk->idx));
+ if (ret) {
+ dev_err(clk->dev,
+ "timed out waiting for reset request to clear\n");
+ return ret;
+ }
+
+ rstctl &= ~PLLaRSTCTL_RSTREQ;
+ rstctl |= PLLaRSTCTL_SDEN | PLLaRSTCTL_PLLRST_B | PLLaRSTCTL_SDRST_B;
+ lynx_write(clk, rstctl, PLLaRSTCTL(clk->idx));
+ ret = read_poll_timeout(lynx_read, rstctl,
+ rstctl & (PLLaRSTCTL_RST_DONE | PLLaRSTCTL_RST_ERR),
+ 100, 5000, true, clk, PLLaRSTCTL(clk->idx));
+ if (ret) {
+ dev_err(clk->dev, "timed out waiting for lock\n");
+ return ret;
+ }
+ return rstctl & PLLaRSTCTL_RST_ERR ? -EIO : 0;
+}
+
+static int lynx_pll_is_enabled(struct clk_hw *hw)
+{
+ struct lynx_clk *clk = lynx_pll_to_clk(hw);
+ u32 rstctl = lynx_read(clk, PLLaRSTCTL(clk->idx));
+
+ dev_dbg(clk->dev, "%s(pll%d)\n", __func__, clk->idx);
+
+ return (rstctl & PLLaRSTCTL_ENABLE_MASK) == PLLaRSTCTL_ENABLE_SET;
+}
+
+static const u32 rfclk_sel_map[8] = {
+ [0b000] = 100000000,
+ [0b001] = 125000000,
+ [0b010] = 156250000,
+ [0b011] = 150000000,
+};
+
+/**
+ * lynx_rfclk_to_sel() - Convert a reference clock rate to a selector
+ * @rate: The reference clock rate
+ *
+ * To allow for some variation in the reference clock rate, up to 100ppm of
+ * error is allowed.
+ *
+ * Return: An appropriate selector for @rate, or -%EINVAL.
+ */
+static int lynx_rfclk_to_sel(u32 rate)
+{
+ int ret;
+
+ for (ret = 0; ret < ARRAY_SIZE(rfclk_sel_map); ret++) {
+ u32 rfclk_rate = rfclk_sel_map[ret];
+ /* Allow an error of 100ppm */
+ u32 error = rfclk_rate / 10000;
+
+ if (rate > rfclk_rate - error && rate < rfclk_rate + error)
+ return ret;
+ }
+
+ return -EINVAL;
+}
+
+static const u32 frate_sel_map[16] = {
+ [0b0000] = 5000000,
+ [0b0101] = 3750000,
+ [0b0110] = 5156250,
+ [0b0111] = 4000000,
+ [0b1001] = 3125000,
+ [0b1010] = 3000000,
+};
+
+/**
+ * lynx_frate_to_sel() - Convert a VCO clock rate to a selector
+ * @rate_khz: The VCO frequency, in kHz
+ *
+ * Return: An appropriate selector for @rate_khz, or -%EINVAL.
+ */
+static int lynx_frate_to_sel(u32 rate_khz)
+{
+ int ret;
+
+ for (ret = 0; ret < ARRAY_SIZE(frate_sel_map); ret++)
+ if (frate_sel_map[ret] == rate_khz)
+ return ret;
+
+ return -EINVAL;
+}
+
+static u32 lynx_pll_ratio(u32 frate_sel, u32 rfclk_sel)
+{
+ u64 frate;
+ u32 rfclk, error, ratio;
+
+ frate = frate_sel_map[frate_sel] * (u64)HZ_PER_KHZ;
+ rfclk = rfclk_sel_map[rfclk_sel];
+
+ if (!frate || !rfclk)
+ return 0;
+
+ ratio = div_u64_rem(frate, rfclk, &error);
+ if (!error)
+ return ratio;
+ return 0;
+}
+
+static unsigned long lynx_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct lynx_clk *clk = lynx_pll_to_clk(hw);
+ u32 cr0 = lynx_read(clk, PLLaCR0(clk->idx));
+ u32 frate_sel = FIELD_GET(PLLaCR0_FRATE_SEL, cr0);
+ u32 rfclk_sel = FIELD_GET(PLLaCR0_RFCLK_SEL, cr0);
+ unsigned long ret;
+
+ dev_dbg(clk->dev, "%s(pll%d, %lu)\n", __func__,
+ clk->idx, parent_rate);
+
+ ret = mult_frac(parent_rate, lynx_pll_ratio(frate_sel, rfclk_sel),
+ HZ_PER_KHZ);
+ return ret;
+}
+
+static long lynx_pll_round_rate(struct clk_hw *hw, unsigned long rate_khz,
+ unsigned long *parent_rate)
+{
+ int frate_sel, rfclk_sel;
+ struct lynx_clk *clk = lynx_pll_to_clk(hw);
+ u32 ratio;
+
+ dev_dbg(clk->dev, "%s(pll%d, %lu, %lu)\n", __func__,
+ clk->idx, rate_khz, *parent_rate);
+
+ frate_sel = lynx_frate_to_sel(rate_khz);
+ if (frate_sel < 0)
+ return frate_sel;
+
+ rfclk_sel = lynx_rfclk_to_sel(*parent_rate);
+ if (rfclk_sel >= 0) {
+ ratio = lynx_pll_ratio(frate_sel, rfclk_sel);
+ if (ratio)
+ return mult_frac(*parent_rate, ratio, HZ_PER_KHZ);
+ }
+
+ for (rfclk_sel = 0;
+ rfclk_sel < ARRAY_SIZE(rfclk_sel_map);
+ rfclk_sel++) {
+ ratio = lynx_pll_ratio(frate_sel, rfclk_sel);
+ if (ratio) {
+ *parent_rate = rfclk_sel_map[rfclk_sel];
+ return mult_frac(*parent_rate, ratio, HZ_PER_KHZ);
+ }
+ }
+
+ return -EINVAL;
+}
+
+static int lynx_pll_set_rate(struct clk_hw *hw, unsigned long rate_khz,
+ unsigned long parent_rate)
+{
+ int frate_sel, rfclk_sel, ret;
+ struct lynx_clk *clk = lynx_pll_to_clk(hw);
+ u32 ratio, cr0 = lynx_read(clk, PLLaCR0(clk->idx));
+
+ dev_dbg(clk->dev, "%s(pll%d, %lu, %lu)\n", __func__,
+ clk->idx, rate_khz, parent_rate);
+
+ frate_sel = lynx_frate_to_sel(rate_khz);
+ if (frate_sel < 0)
+ return frate_sel;
+
+ /* First try the existing rate */
+ rfclk_sel = lynx_rfclk_to_sel(parent_rate);
+ if (rfclk_sel >= 0) {
+ ratio = lynx_pll_ratio(frate_sel, rfclk_sel);
+ if (ratio)
+ goto got_rfclk;
+ }
+
+ for (rfclk_sel = 0;
+ rfclk_sel < ARRAY_SIZE(rfclk_sel_map);
+ rfclk_sel++) {
+ ratio = lynx_pll_ratio(frate_sel, rfclk_sel);
+ if (ratio) {
+ ret = clk_set_rate(clk->ref, rfclk_sel_map[rfclk_sel]);
+ if (!ret)
+ goto got_rfclk;
+ }
+ }
+
+ return ret;
+
+got_rfclk:
+ cr0 &= ~(PLLaCR0_RFCLK_SEL | PLLaCR0_FRATE_SEL);
+ cr0 |= FIELD_PREP(PLLaCR0_RFCLK_SEL, rfclk_sel);
+ cr0 |= FIELD_PREP(PLLaCR0_FRATE_SEL, frate_sel);
+ lynx_write(clk, cr0, PLLaCR0(clk->idx));
+ return 0;
+}
+
+static const struct clk_ops lynx_pll_clk_ops = {
+ .prepare = lynx_pll_prepare,
+ .disable = lynx_pll_disable,
+ .is_enabled = lynx_pll_is_enabled,
+ .recalc_rate = lynx_pll_recalc_rate,
+ .round_rate = lynx_pll_round_rate,
+ .set_rate = lynx_pll_set_rate,
+};
+
+static void lynx_ex_dly_disable(struct clk_hw *hw)
+{
+ struct lynx_clk *clk = lynx_ex_dly_to_clk(hw);
+ u32 cr0 = lynx_read(clk, PLLaCR0(clk->idx));
+
+ cr0 &= ~PLLaCR0_DLYDIV_SEL;
+ lynx_write(clk, PLLaCR0(clk->idx), cr0);
+}
+
+static int lynx_ex_dly_enable(struct clk_hw *hw)
+{
+ struct lynx_clk *clk = lynx_ex_dly_to_clk(hw);
+ u32 cr0 = lynx_read(clk, PLLaCR0(clk->idx));
+
+ cr0 &= ~PLLaCR0_DLYDIV_SEL;
+ cr0 |= FIELD_PREP(PLLaCR0_DLYDIV_SEL, PLLaCR0_DLYDIV_SEL_16);
+ lynx_write(clk, PLLaCR0(clk->idx), cr0);
+ return 0;
+}
+
+static int lynx_ex_dly_is_enabled(struct clk_hw *hw)
+{
+ struct lynx_clk *clk = lynx_ex_dly_to_clk(hw);
+
+ return lynx_read(clk, PLLaCR0(clk->idx)) & PLLaCR0_DLYDIV_SEL;
+}
+
+static unsigned long lynx_ex_dly_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return parent_rate / 16;
+}
+
+static const struct clk_ops lynx_ex_dly_clk_ops = {
+ .enable = lynx_ex_dly_enable,
+ .disable = lynx_ex_dly_disable,
+ .is_enabled = lynx_ex_dly_is_enabled,
+ .recalc_rate = lynx_ex_dly_recalc_rate,
+};
+
+static int lynx_clk_init(struct lynx_clk *clk, struct device *dev,
+ struct regmap *regmap, unsigned int index)
+{
+ const struct clk_hw *pll_parents, *ex_dly_parents;
+ struct clk_init_data pll_init = {
+ .ops = &lynx_pll_clk_ops,
+ .parent_hws = &pll_parents,
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_GATE | CLK_GET_RATE_NOCACHE |
+ CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+ };
+ struct clk_init_data ex_dly_init = {
+ .ops = &lynx_ex_dly_clk_ops,
+ .parent_hws = &ex_dly_parents,
+ .num_parents = 1,
+ };
+ char *ref_name;
+ int ret;
+
+ clk->dev = dev;
+ clk->regmap = regmap;
+ clk->idx = index;
+
+ ref_name = kasprintf(GFP_KERNEL, "ref%d", index);
+ pll_init.name = kasprintf(GFP_KERNEL, "%s.pll%d", dev_name(dev), index);
+ ex_dly_init.name = kasprintf(GFP_KERNEL, "%s_ex_dly", pll_init.name);
+ if (!ref_name || !pll_init.name || !ex_dly_init.name) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ clk->ref = devm_clk_get(dev, ref_name);
+ if (IS_ERR(clk->ref)) {
+ ret = PTR_ERR(clk->ref);
+ dev_err_probe(dev, ret, "could not get %s\n", ref_name);
+ goto out;
+ }
+
+ pll_parents = __clk_get_hw(clk->ref);
+ clk->pll.init = &pll_init;
+ ret = devm_clk_hw_register(dev, &clk->pll);
+ if (ret) {
+ dev_err_probe(dev, ret, "could not register %s\n",
+ pll_init.name);
+ goto out;
+ }
+
+ ex_dly_parents = &clk->pll;
+ clk->ex_dly.init = &ex_dly_init;
+ ret = devm_clk_hw_register(dev, &clk->ex_dly);
+ if (ret)
+ dev_err_probe(dev, ret, "could not register %s\n",
+ ex_dly_init.name);
+
+out:
+ kfree(ref_name);
+ kfree(pll_init.name);
+ kfree(ex_dly_init.name);
+ return ret;
+}
+
+static struct clk_hw *lynx_clk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct lynx_clk *clks = data;
+
+ if (clkspec->args_count != 1)
+ return ERR_PTR(-EINVAL);
+
+ if (clkspec->args[0] > 1)
+ return ERR_PTR(-EINVAL);
+
+ return &clks[clkspec->args[0]].pll;
+}
+
+int lynx_clks_init(struct lynx_clk clks[2], struct device *dev,
+ struct regmap *regmap)
+{
+ int ret, i;
+
+ for (i = 0; i < 2; i++) {
+ ret = lynx_clk_init(&clks[i], dev, regmap, i);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(dev, lynx_clk_get, clks);
+ if (ret)
+ dev_err_probe(dev, ret, "could not register clock provider\n");
+ return ret;
+}
diff --git a/drivers/phy/freescale/phy-fsl-lynx-10g.c b/drivers/phy/freescale/phy-fsl-lynx-10g.c
new file mode 100644
index 000000000000..675f919092f1
--- /dev/null
+++ b/drivers/phy/freescale/phy-fsl-lynx-10g.c
@@ -0,0 +1,1297 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Sean Anderson <sean.anderson@seco.com>
+ *
+ * This driver is for the Lynx 10G phys found on many QorIQ devices, including
+ * the Layerscape series.
+ */
+
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/phy.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+#include "lynx-10g.h"
+
+#define PCCR_BASE 0x200
+#define PCCR_STRIDE 0x4
+#define PCCRn(n) (PCCR_BASE + n * PCCR_STRIDE)
+
+#define PCCR0_PEXa_MASK GENMASK(2, 0)
+#define PCCR0_PEXa_SHIFT(a) (28 - (a) * 4)
+
+#define PCCR2_SATAa_MASK GENMASK(2, 0)
+#define PCCR2_SATAa_SHIFT(a) (28 - (a) * 4)
+
+#define PCCR8_SGMIIa_KX BIT(3)
+#define PCCR8_SGMIIa_MASK GENMASK(3, 0)
+#define PCCR8_SGMIIa_SHIFT(a) (28 - (a) * 4)
+
+#define PCCR9_QSGMIIa_MASK GENMASK(2, 0)
+#define PCCR9_QSGMIIa_SHIFT(a) (28 - (a) * 4)
+
+#define PCCRB_XFIa_MASK GENMASK(2, 0)
+#define PCCRB_XFIa_SHIFT(a) (28 - (a) * 4)
+
+#define LANE_BASE 0x800
+#define LANE_STRIDE 0x40
+#define LNm(m, off) (LANE_BASE + (m) * LANE_STRIDE + (off))
+#define LNmGCR0(m) LNm(m, 0x00)
+#define LNmGCR1(m) LNm(m, 0x04)
+#define LNmSSCR0(m) LNm(m, 0x0C)
+#define LNmRECR0(m) LNm(m, 0x10)
+#define LNmRECR1(m) LNm(m, 0x14)
+#define LNmTECR0(m) LNm(m, 0x18)
+#define LNmSSCR1(m) LNm(m, 0x1C)
+#define LNmTTLCR0(m) LNm(m, 0x20)
+
+#define LNmGCR0_RPLL_LES BIT(31)
+#define LNmGCR0_RRAT_SEL GENMASK(29, 28)
+#define LNmGCR0_TPLL_LES BIT(27)
+#define LNmGCR0_TRAT_SEL GENMASK(25, 24)
+#define LNmGCR0_RRST_B BIT(22)
+#define LNmGCR0_TRST_B BIT(21)
+#define LNmGCR0_RX_PD BIT(20)
+#define LNmGCR0_TX_PD BIT(19)
+#define LNmGCR0_IF20BIT_EN BIT(18)
+#define LNmGCR0_FIRST_LANE BIT(16)
+#define LNmGCR0_TTRM_VM_SEL GENMASK(13, 12)
+#define LNmGCR0_PROTS GENMASK(11, 7)
+
+#define LNmGCR0_RAT_SEL_SAME 0b00
+#define LNmGCR0_RAT_SEL_HALF 0b01
+#define LNmGCR0_RAT_SEL_QUARTER 0b10
+#define LNmGCR0_RAT_SEL_DOUBLE 0b11
+
+#define LNmGCR0_PROTS_PCIE 0b00000
+#define LNmGCR0_PROTS_SGMII 0b00001
+#define LNmGCR0_PROTS_SATA 0b00010
+#define LNmGCR0_PROTS_XFI 0b01010
+
+#define LNmGCR1_RDAT_INV BIT(31)
+#define LNmGCR1_TDAT_INV BIT(30)
+#define LNmGCR1_OPAD_CTL BIT(26)
+#define LNmGCR1_REIDL_TH GENMASK(22, 20)
+#define LNmGCR1_REIDL_EX_SEL GENMASK(19, 18)
+#define LNmGCR1_REIDL_ET_SEL GENMASK(17, 16)
+#define LNmGCR1_REIDL_EX_MSB BIT(15)
+#define LNmGCR1_REIDL_ET_MSB BIT(14)
+#define LNmGCR1_REQ_CTL_SNP BIT(13)
+#define LNmGCR1_REQ_CDR_SNP BIT(12)
+#define LNmGCR1_TRSTDIR BIT(7)
+#define LNmGCR1_REQ_BIN_SNP BIT(6)
+#define LNmGCR1_ISLEW_RCTL GENMASK(5, 4)
+#define LNmGCR1_OSLEW_RCTL GENMASK(1, 0)
+
+#define LNmRECR0_RXEQ_BST BIT(28)
+#define LNmRECR0_GK2OVD GENMASK(27, 24)
+#define LNmRECR0_GK3OVD GENMASK(19, 16)
+#define LNmRECR0_GK2OVD_EN BIT(15)
+#define LNmRECR0_GK3OVD_EN BIT(14)
+#define LNmRECR0_OSETOVD_EN BIT(13)
+#define LNmRECR0_BASE_WAND GENMASK(11, 10)
+#define LNmRECR0_OSETOVD GENMASK(6, 0)
+
+#define LNmRECR0_BASE_WAND_OFF 0b00
+#define LNmRECR0_BASE_WAND_DEFAULT 0b01
+#define LNmRECR0_BASE_WAND_ALTERNATE 0b10
+#define LNmRECR0_BASE_WAND_OSETOVD 0b11
+
+#define LNmTECR0_TEQ_TYPE GENMASK(29, 28)
+#define LNmTECR0_SGN_PREQ BIT(26)
+#define LNmTECR0_RATIO_PREQ GENMASK(25, 22)
+#define LNmTECR0_SGN_POST1Q BIT(21)
+#define LNmTECR0_RATIO_PST1Q GENMASK(20, 16)
+#define LNmTECR0_ADPT_EQ GENMASK(13, 8)
+#define LNmTECR0_AMP_RED GENMASK(5, 0)
+
+#define LNmTECR0_TEQ_TYPE_NONE 0b00
+#define LNmTECR0_TEQ_TYPE_PRE 0b01
+#define LNmTECR0_TEQ_TYPE_BOTH 0b10
+
+#define LNmTTLCR0_FLT_SEL GENMASK(29, 24)
+
+#define PCS_STRIDE 0x10
+#define CR_STRIDE 0x4
+#define PCSa(a, base, cr) (base + (a) * PCS_STRIDE + (cr) * CR_STRIDE)
+
+#define PCSaCR1_MDEV_PORT GENMASK(31, 27)
+
+#define SGMII_BASE 0x1800
+#define SGMIIaCR1(a) PCSa(a, SGMII_BASE, 1)
+
+#define SGMIIaCR1_SGPCS_EN BIT(11)
+
+#define QSGMII_OFFSET 0x1880
+#define QSGMIIaCR1(a) PCSa(a, QSGMII_BASE, 1)
+
+#define XFI_OFFSET 0x1980
+#define XFIaCR1(a) PCSa(a, XFI_BASE, 1)
+
+enum lynx_protocol {
+ LYNX_PROTO_NONE = 0,
+ LYNX_PROTO_SGMII,
+ LYNX_PROTO_SGMII25, /* Not tested */
+ LYNX_PROTO_1000BASEKX, /* Not tested */
+ LYNX_PROTO_QSGMII, /* Not tested */
+ LYNX_PROTO_XFI,
+ LYNX_PROTO_10GKR, /* Link training unimplemented */
+ LYNX_PROTO_PCIE, /* Not implemented */
+ LYNX_PROTO_SATA, /* Not implemented */
+ LYNX_PROTO_LAST,
+};
+
+static const char lynx_proto_str[][16] = {
+ [LYNX_PROTO_NONE] = "unknown",
+ [LYNX_PROTO_SGMII] = "SGMII",
+ [LYNX_PROTO_SGMII25] = "2.5G SGMII",
+ [LYNX_PROTO_1000BASEKX] = "1000BASE-KX",
+ [LYNX_PROTO_QSGMII] = "QSGMII",
+ [LYNX_PROTO_XFI] = "XFI",
+ [LYNX_PROTO_10GKR] = "10GBASE-KR",
+ [LYNX_PROTO_PCIE] = "PCIe",
+ [LYNX_PROTO_SATA] = "SATA",
+};
+
+#define PROTO_MASK(proto) BIT(LYNX_PROTO_##proto)
+#define UNSUPPORTED_PROTOS (PROTO_MASK(SATA) | PROTO_MASK(PCIE))
+
+/**
+ * struct lynx_proto_params - Parameters for configuring a protocol
+ * @frate_khz: The PLL rate, in kHz
+ * @rat_sel: The divider to get the line rate
+ * @if20bit: Whether the proto is 20 bits or 10 bits
+ * @prots: Lane protocol select
+ * @reidl_th: Receiver electrical idle detection threshold
+ * @reidl_ex: Exit electrical idle filter
+ * @reidl_et: Enter idle filter
+ * @slew: Slew control
+ * @baseline_wander: Enable baseline wander correction
+ * @gain: Adaptive equalization gain override
+ * @offset_override: Adaptive equalization offset override
+ * @teq: Transmit equalization type (none, precursor, or precursor and
+ * postcursor). The next few values are only used for appropriate
+ * equalization types.
+ * @preq_ratio: Ratio of full swing transition bit to pre-cursor
+ * @postq_ratio: Ratio of full swing transition bit to first post-cursor.
+ * @adpt_eq: Transmitter Adjustments for 8G/10G
+ * @amp_red: Overall TX Amplitude Reduction
+ * @flt_sel: TTL configuration selector
+ */
+struct lynx_proto_params {
+ u32 frate_khz;
+ u8 rat_sel;
+ u8 prots;
+ u8 reidl_th;
+ u8 reidl_ex;
+ u8 reidl_et;
+ u8 slew;
+ u8 gain;
+ u8 baseline_wander;
+ u8 offset_override;
+ u8 teq;
+ u8 preq_ratio;
+ u8 postq_ratio;
+ u8 adpt_eq;
+ u8 amp_red;
+ u8 flt_sel;
+ bool if20bit;
+};
+
+static const struct lynx_proto_params lynx_proto_params[] = {
+ [LYNX_PROTO_SGMII] = {
+ .frate_khz = 5000000,
+ .rat_sel = LNmGCR0_RAT_SEL_QUARTER,
+ .if20bit = false,
+ .prots = LNmGCR0_PROTS_SGMII,
+ .reidl_th = 0b001,
+ .reidl_ex = 0b011,
+ .reidl_et = 0b100,
+ .slew = 0b01,
+ .gain = 0b1111,
+ .offset_override = 0b0011111,
+ .teq = LNmTECR0_TEQ_TYPE_NONE,
+ .adpt_eq = 0b110000,
+ .amp_red = 0b000110,
+ .flt_sel = 0b111001,
+ },
+ [LYNX_PROTO_1000BASEKX] = {
+ .frate_khz = 5000000,
+ .rat_sel = LNmGCR0_RAT_SEL_QUARTER,
+ .if20bit = false,
+ .prots = LNmGCR0_PROTS_SGMII,
+ .slew = 0b01,
+ .gain = 0b1111,
+ .offset_override = 0b0011111,
+ .teq = LNmTECR0_TEQ_TYPE_NONE,
+ .adpt_eq = 0b110000,
+ .flt_sel = 0b111001,
+ },
+ [LYNX_PROTO_SGMII25] = {
+ .frate_khz = 3125000,
+ .rat_sel = LNmGCR0_RAT_SEL_SAME,
+ .if20bit = false,
+ .prots = LNmGCR0_PROTS_SGMII,
+ .slew = 0b10,
+ .offset_override = 0b0011111,
+ .teq = LNmTECR0_TEQ_TYPE_PRE,
+ .postq_ratio = 0b00110,
+ .adpt_eq = 0b110000,
+ },
+ [LYNX_PROTO_QSGMII] = {
+ .frate_khz = 5000000,
+ .rat_sel = LNmGCR0_RAT_SEL_SAME,
+ .if20bit = true,
+ .prots = LNmGCR0_PROTS_SGMII,
+ .slew = 0b01,
+ .offset_override = 0b0011111,
+ .teq = LNmTECR0_TEQ_TYPE_PRE,
+ .postq_ratio = 0b00110,
+ .adpt_eq = 0b110000,
+ .amp_red = 0b000010,
+ },
+ [LYNX_PROTO_XFI] = {
+ .frate_khz = 5156250,
+ .rat_sel = LNmGCR0_RAT_SEL_DOUBLE,
+ .if20bit = true,
+ .prots = LNmGCR0_PROTS_XFI,
+ .slew = 0b01,
+ .baseline_wander = LNmRECR0_BASE_WAND_DEFAULT,
+ .offset_override = 0b1011111,
+ .teq = LNmTECR0_TEQ_TYPE_PRE,
+ .postq_ratio = 0b00011,
+ .adpt_eq = 0b110000,
+ .amp_red = 0b000111,
+ },
+ [LYNX_PROTO_10GKR] = {
+ .frate_khz = 5156250,
+ .rat_sel = LNmGCR0_RAT_SEL_DOUBLE,
+ .prots = LNmGCR0_PROTS_XFI,
+ .slew = 0b01,
+ .baseline_wander = LNmRECR0_BASE_WAND_DEFAULT,
+ .offset_override = 0b1011111,
+ .teq = LNmTECR0_TEQ_TYPE_BOTH,
+ .preq_ratio = 0b0011,
+ .postq_ratio = 0b01100,
+ .adpt_eq = 0b110000,
+ },
+};
+
+/**
+ * struct lynx_mode - A single configuration of a protocol controller
+ * @protos: A bitmask of the &enum lynx_protocol this mode supports
+ * @first_lane: the first lane which will be used when this config is selected
+ * @last_lane: the last lane which will be used when this config is selected
+ * @pccr: The number of the PCCR which contains this mode
+ * @idx: The index of the protocol controller. For example, SGMIIB would have
+ * index 1.
+ * @cfg: The value to program into the controller to select this mode
+ *
+ * The serdes has multiple protocol controllers which can be each be selected
+ * independently. Depending on their configuration, they may use multiple lanes
+ * at once (e.g. AUI or PCIe x4). Additionally, multiple protocols may be
+ * supported by a single mode (XFI and 10GKR differ only in their protocol
+ * parameters).
+ */
+struct lynx_mode {
+ u16 protos;
+ u8 first_lane;
+ u8 last_lane;
+ u8 pccr;
+ u8 idx;
+ u8 cfg;
+};
+
+static_assert(LYNX_PROTO_LAST - 1 <=
+ sizeof_field(struct lynx_mode, protos) * BITS_PER_BYTE);
+
+/**
+ * enum lynx_caps - serdes hardware capabilities
+ * @LYNX_HAS_1000BASEKX: 1000BASE-KX supported
+ * @LYNX_HAS_10GKR: 10GBASE-KR supported
+ */
+enum lynx_caps {
+ LYNX_HAS_1000BASEKX,
+ LYNX_HAS_10GKR,
+};
+
+/**
+ * struct lynx_conf - Configuration for a particular serdes
+ * @lanes: Number of lanes
+ * @caps: A bitmask of &enum lynx_caps
+ * @endian: Endianness of the registers
+ */
+struct lynx_conf {
+ unsigned int lanes;
+ unsigned int caps;
+ enum regmap_endian endian;
+};
+
+struct lynx_priv;
+
+/**
+ * struct lynx_priv - Driver data for the serdes
+ * @lock: A lock protecting "common" registers in @regmap, as well as the
+ * members of this struct. Lane-specific registers are protected by the
+ * phy's lock. PLL registers are protected by the clock's lock.
+ * @clks: The PLL clocks
+ * @dev: The serdes device
+ * @regmap: The backing regmap
+ * @conf: The configuration for this serdes
+ * @modes: Valid protocol controller configurations
+ * @mode_count: Number of modes in @modes
+ * @used_lanes: Bitmap of the lanes currently used by phys
+ * @groups: List of the created groups
+ */
+struct lynx_priv {
+ struct mutex lock;
+ struct lynx_clk clks[2];
+ struct device *dev;
+ struct regmap *regmap;
+ const struct lynx_conf *conf;
+ const struct lynx_mode *modes;
+ size_t mode_count;
+ unsigned int used_lanes;
+ struct list_head groups;
+};
+
+/**
+ * struct lynx_group - Driver data for a group of lanes
+ * @groups: List of other groups; protected by @serdes->lock.
+ * @phy: The associated phy
+ * @serdes: The parent serdes
+ * @pll: The currently-used pll
+ * @ex_dly: The ex_dly clock, if used
+ * @first_lane: The first lane in the group
+ * @last_lane: The last lane in the group
+ * @proto: The currently-configured protocol
+ * @users: Number of current users; protected by @serdes->lock.
+ */
+struct lynx_group {
+ struct list_head groups;
+ struct phy *phy;
+ struct lynx_priv *serdes;
+ struct clk *pll;
+ struct clk *ex_dly;
+ unsigned int first_lane;
+ unsigned int last_lane;
+ enum lynx_protocol proto;
+ unsigned int users;
+};
+
+static u32 lynx_read(struct lynx_priv *serdes, u32 reg)
+{
+ unsigned int ret = 0;
+
+ WARN_ON_ONCE(regmap_read(serdes->regmap, reg, &ret));
+ return ret;
+}
+
+static void lynx_write(struct lynx_priv *serdes, u32 val, u32 reg)
+{
+ WARN_ON_ONCE(regmap_write(serdes->regmap, reg, val));
+}
+
+/**
+ * lynx_lane_bitmap() - Get a bitmap for a group of lanes
+ * @group: The group of lanes
+ *
+ * Return: A mask containing all bits between @group->first and @group->last
+ */
+static unsigned int lynx_lane_bitmap(struct lynx_group *group)
+{
+ if (group->first_lane > group->last_lane)
+ return GENMASK(group->first_lane, group->last_lane);
+ else
+ return GENMASK(group->last_lane, group->first_lane);
+}
+
+static int lynx_init(struct phy *phy)
+{
+ int ret = 0;
+ struct lynx_group *group = phy_get_drvdata(phy);
+ struct lynx_priv *serdes = group->serdes;
+ unsigned int lane_mask = lynx_lane_bitmap(group);
+
+ mutex_lock(&serdes->lock);
+ if (serdes->used_lanes & lane_mask)
+ ret = -EBUSY;
+ else
+ serdes->used_lanes |= lane_mask;
+ mutex_unlock(&serdes->lock);
+ return ret;
+}
+
+static int lynx_exit(struct phy *phy)
+{
+ struct lynx_group *group = phy_get_drvdata(phy);
+ struct lynx_priv *serdes = group->serdes;
+
+ clk_disable_unprepare(group->ex_dly);
+ group->ex_dly = NULL;
+
+ clk_disable_unprepare(group->pll);
+ clk_rate_exclusive_put(group->pll);
+ group->pll = NULL;
+
+ mutex_lock(&serdes->lock);
+ serdes->used_lanes &= ~lynx_lane_bitmap(group);
+ mutex_unlock(&serdes->lock);
+ return 0;
+}
+
+/*
+ * This is tricky. If first_lane=1 and last_lane=0, the condition will see 2,
+ * 1, 0. But the loop body will see 1, 0. We do this to avoid underflow. We
+ * can't pull the same trick when incrementing, because then we might have to
+ * start at -1 if (e.g.) first_lane = 0.
+ */
+#define for_range(val, start, end) \
+ for (val = start < end ? start : start + 1; \
+ start < end ? val <= end : val-- > end; \
+ start < end ? val++ : 0)
+#define for_each_lane(lane, group) \
+ for_range(lane, group->first_lane, group->last_lane)
+#define for_each_lane_reverse(lane, group) \
+ for_range(lane, group->last_lane, group->first_lane)
+
+static int lynx_power_on(struct phy *phy)
+{
+ int i;
+ struct lynx_group *group = phy_get_drvdata(phy);
+ u32 gcr0;
+
+ for_each_lane(i, group) {
+ gcr0 = lynx_read(group->serdes, LNmGCR0(i));
+ gcr0 &= ~(LNmGCR0_RX_PD | LNmGCR0_TX_PD);
+ lynx_write(group->serdes, gcr0, LNmGCR0(i));
+
+ usleep_range(15, 30);
+ gcr0 |= LNmGCR0_RRST_B | LNmGCR0_TRST_B;
+ lynx_write(group->serdes, gcr0, LNmGCR0(i));
+ }
+
+ return 0;
+}
+
+static void lynx_power_off_lane(struct lynx_priv *serdes, unsigned int lane)
+{
+ u32 gcr0 = lynx_read(serdes, LNmGCR0(lane));
+
+ gcr0 |= LNmGCR0_RX_PD | LNmGCR0_TX_PD;
+ gcr0 &= ~(LNmGCR0_RRST_B | LNmGCR0_TRST_B);
+ lynx_write(serdes, gcr0, LNmGCR0(lane));
+}
+
+static int lynx_power_off(struct phy *phy)
+{
+ unsigned int i;
+ struct lynx_group *group = phy_get_drvdata(phy);
+
+ for_each_lane_reverse(i, group)
+ lynx_power_off_lane(group->serdes, i);
+
+ return 0;
+}
+
+/**
+ * lynx_lookup_proto() - Convert a phy-subsystem mode to a protocol
+ * @mode: The mode to convert
+ * @submode: The submode of @mode
+ *
+ * Return: A corresponding serdes-specific mode
+ */
+static enum lynx_protocol lynx_lookup_proto(enum phy_mode mode, int submode)
+{
+ switch (mode) {
+ case PHY_MODE_ETHERNET:
+ switch (submode) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ return LYNX_PROTO_SGMII;
+ case PHY_INTERFACE_MODE_1000BASEKX:
+ return LYNX_PROTO_1000BASEKX;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ return LYNX_PROTO_SGMII25;
+ case PHY_INTERFACE_MODE_QSGMII:
+ return LYNX_PROTO_QSGMII;
+ case PHY_INTERFACE_MODE_XGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ return LYNX_PROTO_XFI;
+ case PHY_INTERFACE_MODE_10GKR:
+ return LYNX_PROTO_10GKR;
+ default:
+ return LYNX_PROTO_NONE;
+ }
+ /* Not implemented (yet) */
+ case PHY_MODE_PCIE:
+ case PHY_MODE_SATA:
+ default:
+ return LYNX_PROTO_NONE;
+ }
+}
+
+/**
+ * lynx_lookup_mode() - Get the mode for a group/protocol combination
+ * @group: The group of lanes to use
+ * @proto: The protocol to use
+ *
+ * Return: An appropriate mode to use, or %NULL if none match.
+ */
+static const struct lynx_mode *lynx_lookup_mode(struct lynx_group *group,
+ enum lynx_protocol proto)
+{
+ int i;
+ const struct lynx_priv *serdes = group->serdes;
+
+ for (i = 0; i < serdes->mode_count; i++) {
+ const struct lynx_mode *mode = &serdes->modes[i];
+
+ if (BIT(proto) & mode->protos &&
+ group->first_lane == mode->first_lane &&
+ group->last_lane == mode->last_lane)
+ return mode;
+ }
+
+ return NULL;
+}
+
+static int lynx_validate(struct phy *phy, enum phy_mode phy_mode, int submode,
+ union phy_configure_opts *opts)
+{
+ enum lynx_protocol proto;
+ struct lynx_group *group = phy_get_drvdata(phy);
+ const struct lynx_mode *mode;
+
+ proto = lynx_lookup_proto(phy_mode, submode);
+ if (proto == LYNX_PROTO_NONE)
+ return -EINVAL;
+
+ /* Nothing to do */
+ if (proto == group->proto)
+ return 0;
+
+ mode = lynx_lookup_mode(group, proto);
+ if (!mode)
+ return -EINVAL;
+
+ return 0;
+}
+
+/**
+ * lynx_proto_mode_mask() - Get the mask for a PCCR config
+ * @mode: The mode to use
+ *
+ * Return: The mask, shifted down to the lsb.
+ */
+static u32 lynx_proto_mode_mask(const struct lynx_mode *mode)
+{
+ switch (mode->pccr) {
+ case 0x0:
+ if (mode->protos & PROTO_MASK(PCIE))
+ return PCCR0_PEXa_MASK;
+ break;
+ case 0x2:
+ if (mode->protos & PROTO_MASK(SATA))
+ return PCCR2_SATAa_MASK;
+ break;
+ case 0x8:
+ if (mode->protos & PROTO_MASK(SGMII))
+ return PCCR8_SGMIIa_MASK;
+ break;
+ case 0x9:
+ if (mode->protos & PROTO_MASK(QSGMII))
+ return PCCR9_QSGMIIa_MASK;
+ break;
+ case 0xB:
+ if (mode->protos & PROTO_MASK(XFI))
+ return PCCRB_XFIa_MASK;
+ break;
+ }
+ pr_err("unknown mode PCCR%X %s%c\n", mode->pccr,
+ lynx_proto_str[mode->protos], 'A' + mode->idx);
+ return 0;
+}
+
+/**
+ * lynx_proto_mode_shift() - Get the shift for a PCCR config
+ * @mode: The mode to use
+ *
+ * Return: The amount of bits to shift the mask.
+ */
+static u32 lynx_proto_mode_shift(const struct lynx_mode *mode)
+{
+ switch (mode->pccr) {
+ case 0x0:
+ if (mode->protos & PROTO_MASK(PCIE))
+ return PCCR0_PEXa_SHIFT(mode->idx);
+ break;
+ case 0x2:
+ if (mode->protos & PROTO_MASK(SATA))
+ return PCCR2_SATAa_SHIFT(mode->idx);
+ break;
+ case 0x8:
+ if (mode->protos & PROTO_MASK(SGMII))
+ return PCCR8_SGMIIa_SHIFT(mode->idx);
+ break;
+ case 0x9:
+ if (mode->protos & PROTO_MASK(QSGMII))
+ return PCCR9_QSGMIIa_SHIFT(mode->idx);
+ break;
+ case 0xB:
+ if (mode->protos & PROTO_MASK(XFI))
+ return PCCRB_XFIa_SHIFT(mode->idx);
+ break;
+ }
+ pr_err("unknown mode PCCR%X %s%c\n", mode->pccr,
+ lynx_proto_str[mode->protos], 'A' + mode->idx);
+ return 0;
+}
+
+/**
+ * lynx_proto_mode_get() - Get the current config for a PCCR mode
+ * @mode: The mode to use
+ * @pccr: The current value of the PCCR
+ *
+ * Return: The current value of the PCCR config for this mode
+ */
+static u32 lynx_proto_mode_get(const struct lynx_mode *mode, u32 pccr)
+{
+ return (pccr >> lynx_proto_mode_shift(mode)) &
+ lynx_proto_mode_mask(mode);
+}
+
+/**
+ * lynx_proto_mode_prep() - Configure a PCCR for a protocol
+ * @mode: The mode to use
+ * @pccr: The current value of the PCCR
+ * @proto: The protocol to configure
+ *
+ * This configures a PCCR for a mode and protocol. To disable a mode, pass
+ * %LYNX_PROTO_NONE as @proto. If @proto is 1000BASE-KX, then the KX bit
+ * will be set.
+ *
+ * Return: The new value for the PCCR
+ */
+static u32 lynx_proto_mode_prep(const struct lynx_mode *mode, u32 pccr,
+ enum lynx_protocol proto)
+{
+ u32 shift = lynx_proto_mode_shift(mode);
+
+ pccr &= ~(lynx_proto_mode_mask(mode) << shift);
+ if (proto != LYNX_PROTO_NONE)
+ pccr |= mode->cfg << shift;
+
+ if (proto == LYNX_PROTO_1000BASEKX) {
+ if (mode->pccr == 8)
+ pccr |= PCCR8_SGMIIa_KX << shift;
+ else
+ pr_err("PCCR%X doesn't have a KX bit\n", mode->pccr);
+ }
+
+ return pccr;
+}
+
+#define abs_diff(a, b) ({ \
+ typeof(a) _a = (a); \
+ typeof(b) _b = (b); \
+ _a > _b ? _a - _b : _b - _a; \
+})
+
+static int lynx_set_mode(struct phy *phy, enum phy_mode phy_mode, int submode)
+{
+ enum lynx_protocol proto;
+ const struct lynx_proto_params *params;
+ const struct lynx_mode *old_mode = NULL, *new_mode;
+ int i, pll, ret;
+ struct lynx_group *group = phy_get_drvdata(phy);
+ struct lynx_priv *serdes = group->serdes;
+ u32 tmp;
+ u32 gcr0 = 0, gcr1 = 0, recr0 = 0, tecr0 = 0;
+ u32 gcr0_mask = 0, gcr1_mask = 0, recr0_mask = 0, tecr0_mask = 0;
+
+ proto = lynx_lookup_proto(phy_mode, submode);
+ if (proto == LYNX_PROTO_NONE) {
+ dev_dbg(&phy->dev, "unknown mode/submode %d/%d\n",
+ phy_mode, submode);
+ return -EINVAL;
+ }
+
+ /* Nothing to do */
+ if (proto == group->proto)
+ return 0;
+
+ new_mode = lynx_lookup_mode(group, proto);
+ if (!new_mode) {
+ dev_dbg(&phy->dev, "could not find mode for %s on lanes %u to %u\n",
+ lynx_proto_str[proto], group->first_lane,
+ group->last_lane);
+ return -EINVAL;
+ }
+
+ if (group->proto != LYNX_PROTO_NONE) {
+ old_mode = lynx_lookup_mode(group, group->proto);
+ if (!old_mode) {
+ dev_err(&phy->dev, "could not find mode for %s\n",
+ lynx_proto_str[group->proto]);
+ return -EBUSY;
+ }
+ }
+
+ mutex_lock(&serdes->lock);
+
+ tmp = lynx_read(serdes, PCCRn(new_mode->pccr));
+ if (lynx_proto_mode_get(new_mode, tmp)) {
+ mutex_unlock(&serdes->lock);
+ dev_dbg(&phy->dev, "%s%c already in use\n",
+ lynx_proto_str[new_mode->protos], 'A' + new_mode->idx);
+ return -EBUSY;
+ }
+
+ /* Disable the old controller */
+ if (old_mode) {
+ tmp = lynx_read(serdes, PCCRn(old_mode->pccr));
+ tmp = lynx_proto_mode_prep(old_mode, tmp, LYNX_PROTO_NONE);
+ lynx_write(serdes, tmp, PCCRn(old_mode->pccr));
+
+ if (old_mode->protos & PROTO_MASK(SGMII)) {
+ tmp = lynx_read(serdes, SGMIIaCR1(old_mode->idx));
+ tmp &= SGMIIaCR1_SGPCS_EN;
+ lynx_write(serdes, tmp, SGMIIaCR1(old_mode->idx));
+ }
+ }
+ group->proto = LYNX_PROTO_NONE;
+
+ clk_disable_unprepare(group->ex_dly);
+ group->ex_dly = NULL;
+
+ clk_disable_unprepare(group->pll);
+ clk_rate_exclusive_put(group->pll);
+ group->pll = NULL;
+
+ /* First, try to use a PLL which already has the correct rate */
+ params = &lynx_proto_params[proto];
+ for (pll = 0; pll < ARRAY_SIZE(serdes->clks); pll++) {
+ struct clk *clk = serdes->clks[pll].pll.clk;
+ unsigned long rate = clk_get_rate(clk);
+ unsigned long error = abs_diff(rate, params->frate_khz);
+
+ dev_dbg(&phy->dev, "pll%d has rate %lu\n", pll, rate);
+ /* Accept up to 100ppm deviation */
+ if ((!error || params->frate_khz / error > 10000) &&
+ !clk_set_rate_exclusive(clk, rate))
+ goto got_pll;
+ /* Someone else got a different rate first */
+ }
+
+ /* If neither PLL has the right rate, try setting it */
+ for (pll = 0; pll < 2; pll++) {
+ ret = clk_set_rate_exclusive(serdes->clks[pll].pll.clk,
+ params->frate_khz);
+ if (!ret)
+ goto got_pll;
+ }
+
+ dev_dbg(&phy->dev, "could not get a pll at %ukHz\n",
+ params->frate_khz);
+ return ret;
+
+got_pll:
+ group->pll = serdes->clks[pll].pll.clk;
+ clk_prepare_enable(group->pll);
+
+ gcr0_mask |= LNmGCR0_RRAT_SEL | LNmGCR0_TRAT_SEL;
+ gcr0_mask |= LNmGCR0_RPLL_LES | LNmGCR0_TPLL_LES;
+ gcr0_mask |= LNmGCR0_RRST_B | LNmGCR0_TRST_B;
+ gcr0_mask |= LNmGCR0_RX_PD | LNmGCR0_TX_PD;
+ gcr0_mask |= LNmGCR0_IF20BIT_EN | LNmGCR0_PROTS;
+ gcr0 |= FIELD_PREP(LNmGCR0_RPLL_LES, !pll);
+ gcr0 |= FIELD_PREP(LNmGCR0_TPLL_LES, !pll);
+ gcr0 |= FIELD_PREP(LNmGCR0_RRAT_SEL, params->rat_sel);
+ gcr0 |= FIELD_PREP(LNmGCR0_TRAT_SEL, params->rat_sel);
+ gcr0 |= FIELD_PREP(LNmGCR0_IF20BIT_EN, params->if20bit);
+ gcr0 |= FIELD_PREP(LNmGCR0_PROTS, params->prots);
+
+ gcr1_mask |= LNmGCR1_RDAT_INV | LNmGCR1_TDAT_INV;
+ gcr1_mask |= LNmGCR1_OPAD_CTL | LNmGCR1_REIDL_TH;
+ gcr1_mask |= LNmGCR1_REIDL_EX_SEL | LNmGCR1_REIDL_ET_SEL;
+ gcr1_mask |= LNmGCR1_REIDL_EX_MSB | LNmGCR1_REIDL_ET_MSB;
+ gcr1_mask |= LNmGCR1_REQ_CTL_SNP | LNmGCR1_REQ_CDR_SNP;
+ gcr1_mask |= LNmGCR1_TRSTDIR | LNmGCR1_REQ_BIN_SNP;
+ gcr1_mask |= LNmGCR1_ISLEW_RCTL | LNmGCR1_OSLEW_RCTL;
+ gcr1 |= FIELD_PREP(LNmGCR1_REIDL_TH, params->reidl_th);
+ gcr1 |= FIELD_PREP(LNmGCR1_REIDL_EX_SEL, params->reidl_ex & 3);
+ gcr1 |= FIELD_PREP(LNmGCR1_REIDL_ET_SEL, params->reidl_et & 3);
+ gcr1 |= FIELD_PREP(LNmGCR1_REIDL_EX_MSB, params->reidl_ex >> 2);
+ gcr1 |= FIELD_PREP(LNmGCR1_REIDL_ET_MSB, params->reidl_et >> 2);
+ gcr1 |= FIELD_PREP(LNmGCR1_TRSTDIR,
+ group->first_lane > group->last_lane);
+ gcr1 |= FIELD_PREP(LNmGCR1_ISLEW_RCTL, params->slew);
+ gcr1 |= FIELD_PREP(LNmGCR1_OSLEW_RCTL, params->slew);
+
+ recr0_mask |= LNmRECR0_RXEQ_BST | LNmRECR0_BASE_WAND;
+ recr0_mask |= LNmRECR0_GK2OVD | LNmRECR0_GK3OVD;
+ recr0_mask |= LNmRECR0_GK2OVD_EN | LNmRECR0_GK3OVD_EN;
+ recr0_mask |= LNmRECR0_OSETOVD_EN | LNmRECR0_OSETOVD;
+ if (params->gain) {
+ recr0 |= FIELD_PREP(LNmRECR0_GK2OVD, params->gain);
+ recr0 |= FIELD_PREP(LNmRECR0_GK3OVD, params->gain);
+ recr0 |= LNmRECR0_GK2OVD_EN | LNmRECR0_GK3OVD_EN;
+ }
+ recr0 |= FIELD_PREP(LNmRECR0_BASE_WAND, params->baseline_wander);
+ recr0 |= FIELD_PREP(LNmRECR0_OSETOVD, params->offset_override);
+
+ tecr0_mask |= LNmTECR0_TEQ_TYPE;
+ tecr0_mask |= LNmTECR0_SGN_PREQ | LNmTECR0_RATIO_PREQ;
+ tecr0_mask |= LNmTECR0_SGN_POST1Q | LNmTECR0_RATIO_PST1Q;
+ tecr0_mask |= LNmTECR0_ADPT_EQ | LNmTECR0_AMP_RED;
+ tecr0 |= FIELD_PREP(LNmTECR0_TEQ_TYPE, params->teq);
+ if (params->preq_ratio) {
+ tecr0 |= FIELD_PREP(LNmTECR0_SGN_PREQ, 1);
+ tecr0 |= FIELD_PREP(LNmTECR0_RATIO_PREQ, params->preq_ratio);
+ }
+ if (params->postq_ratio) {
+ tecr0 |= FIELD_PREP(LNmTECR0_SGN_POST1Q, 1);
+ tecr0 |= FIELD_PREP(LNmTECR0_RATIO_PST1Q, params->postq_ratio);
+ }
+ tecr0 |= FIELD_PREP(LNmTECR0_ADPT_EQ, params->adpt_eq);
+ tecr0 |= FIELD_PREP(LNmTECR0_AMP_RED, params->amp_red);
+
+ for_each_lane_reverse(i, group) {
+ tmp = lynx_read(serdes, LNmGCR0(i));
+ tmp &= ~(LNmGCR0_RRST_B | LNmGCR0_TRST_B);
+ lynx_write(serdes, tmp, LNmGCR0(i));
+ ndelay(50);
+
+ tmp &= ~gcr0_mask;
+ tmp |= gcr0;
+ tmp |= FIELD_PREP(LNmGCR0_FIRST_LANE, i == group->first_lane);
+ lynx_write(serdes, tmp, LNmGCR0(i));
+
+ tmp = lynx_read(serdes, LNmGCR1(i));
+ tmp &= ~gcr1_mask;
+ tmp |= gcr1;
+ lynx_write(serdes, tmp, LNmGCR1(i));
+
+ tmp = lynx_read(serdes, LNmRECR0(i));
+ tmp &= ~recr0_mask;
+ tmp |= recr0;
+ lynx_write(serdes, tmp, LNmRECR0(i));
+
+ tmp = lynx_read(serdes, LNmTECR0(i));
+ tmp &= ~tecr0_mask;
+ tmp |= tecr0;
+ lynx_write(serdes, tmp, LNmTECR0(i));
+
+ tmp = lynx_read(serdes, LNmTTLCR0(i));
+ tmp &= ~LNmTTLCR0_FLT_SEL;
+ tmp |= FIELD_PREP(LNmTTLCR0_FLT_SEL, params->flt_sel);
+ lynx_write(serdes, tmp, LNmTTLCR0(i));
+
+ ndelay(120);
+ tmp = lynx_read(serdes, LNmGCR0(i));
+ tmp |= LNmGCR0_RRST_B | LNmGCR0_TRST_B;
+ lynx_write(serdes, tmp, LNmGCR0(i));
+ }
+
+ /* Enable the new controller */
+ tmp = lynx_read(serdes, PCCRn(new_mode->pccr));
+ tmp = lynx_proto_mode_prep(new_mode, tmp, proto);
+ lynx_write(serdes, tmp, PCCRn(new_mode->pccr));
+
+ if (proto == LYNX_PROTO_1000BASEKX) {
+ group->ex_dly = serdes->clks[pll].ex_dly.clk;
+ /* This should never fail since it's from our internal driver */
+ WARN_ON_ONCE(clk_prepare_enable(group->ex_dly));
+ }
+
+ if (new_mode->protos & PROTO_MASK(SGMII)) {
+ tmp = lynx_read(serdes, SGMIIaCR1(new_mode->idx));
+ tmp |= SGMIIaCR1_SGPCS_EN;
+ lynx_write(serdes, tmp, SGMIIaCR1(new_mode->idx));
+ }
+
+ mutex_unlock(&serdes->lock);
+
+ group->proto = proto;
+ dev_dbg(&phy->dev, "set mode to %s on lanes %u to %u\n",
+ lynx_proto_str[proto], group->first_lane, group->last_lane);
+ return 0;
+}
+
+static void lynx_release(struct phy *phy)
+{
+ struct lynx_group *group = phy_get_drvdata(phy);
+ struct lynx_priv *serdes = group->serdes;
+
+ mutex_lock(&serdes->lock);
+ if (--group->users) {
+ mutex_unlock(&serdes->lock);
+ return;
+ }
+ list_del(&group->groups);
+ mutex_unlock(&serdes->lock);
+
+ phy_destroy(phy);
+ kfree(group);
+}
+
+static const struct phy_ops lynx_phy_ops = {
+ .init = lynx_init,
+ .exit = lynx_exit,
+ .power_on = lynx_power_on,
+ .power_off = lynx_power_off,
+ .set_mode = lynx_set_mode,
+ .validate = lynx_validate,
+ .release = lynx_release,
+ .owner = THIS_MODULE,
+};
+
+static struct phy *lynx_xlate(struct device *dev, struct of_phandle_args *args)
+{
+ struct phy *phy;
+ struct list_head *head;
+ struct lynx_group *group;
+ struct lynx_priv *serdes = dev_get_drvdata(dev);
+ unsigned int last_lane;
+
+ if (args->args_count == 1)
+ last_lane = args->args[0];
+ else if (args->args_count == 2)
+ last_lane = args->args[1];
+ else
+ return ERR_PTR(-EINVAL);
+
+ mutex_lock(&serdes->lock);
+
+ /* Look for an existing group */
+ list_for_each(head, &serdes->groups) {
+ group = container_of(head, struct lynx_group, groups);
+ if (group->first_lane == args->args[0] &&
+ group->last_lane == last_lane) {
+ group->users++;
+ phy = group->phy;
+ goto out;
+ }
+ }
+
+ /* None found, create our own */
+ group = kzalloc(sizeof(*group), GFP_KERNEL);
+ if (!group) {
+ phy = ERR_PTR(-ENOMEM);
+ goto out;
+ }
+
+ group->serdes = serdes;
+ group->first_lane = args->args[0];
+ group->last_lane = last_lane;
+ group->users = 1;
+ phy = phy_create(dev, NULL, &lynx_phy_ops);
+ if (IS_ERR(phy)) {
+ kfree(group);
+ } else {
+ group->phy = phy;
+ phy_set_drvdata(phy, group);
+ list_add(&group->groups, &serdes->groups);
+ }
+
+out:
+ mutex_unlock(&serdes->lock);
+ return phy;
+}
+
+static int lynx_read_u32(struct device *dev, struct fwnode_handle *fwnode,
+ const char *prop, u32 *val)
+{
+ int ret;
+
+ ret = fwnode_property_read_u32(fwnode, prop, val);
+ if (ret)
+ dev_err(dev, "could not read %s from %pfwP: %d\n", prop,
+ fwnode, ret);
+ return ret;
+}
+
+static int lynx_parse_mode(struct lynx_priv *serdes, struct fwnode_handle *fwnode,
+ struct lynx_mode *mode, u16 protos, u8 pccr, u8 idx)
+{
+ struct device *dev = serdes->dev;
+ int ret;
+ u32 val;
+
+ ret = lynx_read_u32(dev, fwnode, "fsl,cfg", &val);
+ if (ret)
+ return ret;
+ mode->cfg = val;
+
+ ret = lynx_read_u32(dev, fwnode, "fsl,first-lane", &val);
+ if (ret)
+ return ret;
+ mode->first_lane = val;
+
+ ret = fwnode_property_read_u32(fwnode, "fsl,last-lane", &val);
+ if (ret && ret != -EINVAL) {
+ dev_err(dev, "could not read %s from %pfwP: %d\n",
+ "fsl,last-lane", fwnode, ret);
+ return ret;
+ }
+ mode->last_lane = val;
+
+ if (mode->first_lane >= serdes->conf->lanes) {
+ dev_err(dev,
+ "value of %s (%u) in %pfwP exceeds lane count (%u)\n",
+ "fsl,first-lane", mode->first_lane, fwnode,
+ serdes->conf->lanes);
+ return -EINVAL;
+ } else if (mode->last_lane >= serdes->conf->lanes) {
+ dev_err(dev,
+ "value of %s (%u) in %pfwP exceeds lane count (%u)\n",
+ "fsl,last-lane", mode->last_lane, fwnode,
+ serdes->conf->lanes);
+ return -EINVAL;
+ }
+
+ mode->protos = protos;
+ mode->pccr = pccr;
+ mode->idx = idx;
+ return 0;
+}
+
+static int lynx_parse_pccrs(struct lynx_priv *serdes)
+{
+ struct fwnode_handle *pccr_node, *proto_node, *config_node;
+ struct device *dev = serdes->dev;
+ size_t mode = 0, mode_total = 0;
+ struct lynx_mode *modes;
+ int ret;
+
+ /* To ease memory management, calculate our allocation up-front */
+ device_for_each_child_node(dev, pccr_node) {
+ fwnode_for_each_child_node(pccr_node, proto_node) {
+ size_t mode_subtotal = 0;
+
+ fwnode_for_each_child_node(proto_node, config_node)
+ mode_subtotal++;
+ mode_total += mode_subtotal ?: 1;
+ }
+ }
+
+ modes = devm_kcalloc(dev, mode_total, sizeof(*modes),
+ GFP_KERNEL);
+ if (!modes)
+ return -ENOMEM;
+
+ device_for_each_child_node(dev, pccr_node) {
+ u32 pccr;
+
+ lynx_read_u32(dev, pccr_node, "fsl,pccr", &pccr);
+ if (ret)
+ return ret;
+
+ fwnode_for_each_child_node(pccr_node, proto_node) {
+ const char *proto_str;
+ bool children = false;
+ u16 protos;
+ u32 index;
+
+ lynx_read_u32(dev, proto_node, "fsl,index", &index);
+ if (ret)
+ return ret;
+
+ ret = fwnode_property_read_string(proto_node,
+ "fsl,proto",
+ &proto_str);
+ if (ret) {
+ dev_err(dev,
+ "could not read %s from %pfwP: %d\n",
+ "fsl,proto", proto_node, ret);
+ return ret;
+ }
+
+ if (strstarts(proto_str, "sgmii")) {
+ protos = PROTO_MASK(SGMII);
+ if (serdes->conf->caps &
+ BIT(LYNX_HAS_1000BASEKX))
+ protos |= PROTO_MASK(1000BASEKX);
+ if (!strcmp(proto_str, "sgmii25"))
+ protos |= PROTO_MASK(SGMII25);
+ } else if (!strcmp(proto_str, "qsgmii")) {
+ protos = PROTO_MASK(QSGMII);
+ } else if (!strcmp(proto_str, "xfi")) {
+ protos = PROTO_MASK(XFI);
+ if (serdes->conf->caps & BIT(LYNX_HAS_10GKR))
+ protos |= PROTO_MASK(10GKR);
+ } else if (!strcmp(proto_str, "pcie")) {
+ protos = PROTO_MASK(PCIE);
+ } else if (!strcmp(proto_str, "sata")) {
+ protos = PROTO_MASK(SATA);
+ } else {
+ dev_warn(dev,
+ "unknown protocol %s for fsl,proto in %pfwP\n",
+ proto_str, proto_node);
+ continue;
+ }
+
+ fwnode_for_each_child_node(proto_node, config_node) {
+ children = true;
+ ret = lynx_parse_mode(serdes, config_node,
+ &modes[mode++],
+ protos, pccr, index);
+ if (ret)
+ return ret;
+ }
+
+ if (!children) {
+ ret = lynx_parse_mode(serdes, proto_node,
+ &modes[mode++],
+ protos, pccr, index);
+ if (ret)
+ return ret;
+ }
+ }
+ }
+
+ serdes->modes = modes;
+ WARN_ON(mode != mode_total);
+ serdes->mode_count = mode;
+ return 0;
+}
+
+static int lynx_probe(struct platform_device *pdev)
+{
+ bool grabbed_clocks = false;
+ int i, ret;
+ struct device *dev = &pdev->dev;
+ struct lynx_priv *serdes;
+ struct regmap_config regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .disable_locking = true,
+ };
+ struct resource *res;
+ void __iomem *base;
+
+ serdes = devm_kzalloc(dev, sizeof(*serdes), GFP_KERNEL);
+ if (!serdes)
+ return -ENOMEM;
+
+ serdes->dev = dev;
+ platform_set_drvdata(pdev, serdes);
+ mutex_init(&serdes->lock);
+ INIT_LIST_HEAD(&serdes->groups);
+ serdes->conf = device_get_match_data(dev);
+
+ ret = lynx_parse_pccrs(serdes);
+ if (ret)
+ return ret;
+
+ base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(base)) {
+ ret = PTR_ERR(base);
+ dev_err_probe(dev, ret, "could not get/map registers\n");
+ return ret;
+ }
+
+ regmap_config.val_format_endian = serdes->conf->endian;
+ regmap_config.max_register = res->end - res->start;
+ serdes->regmap = devm_regmap_init_mmio(dev, base, ®map_config);
+ if (IS_ERR(serdes->regmap)) {
+ ret = PTR_ERR(serdes->regmap);
+ dev_err_probe(dev, ret, "could not create regmap\n");
+ return ret;
+ }
+
+ ret = lynx_clks_init(serdes->clks, dev, serdes->regmap);
+ if (ret)
+ return ret;
+
+ /* Deselect anything configured by the RCW/bootloader */
+ for (i = 0; i < serdes->mode_count; i++) {
+ const struct lynx_mode *mode = &serdes->modes[i];
+ u32 pccr = lynx_read(serdes, PCCRn(mode->pccr));
+
+ if (lynx_proto_mode_get(mode, pccr) == mode->cfg) {
+ if (mode->protos & UNSUPPORTED_PROTOS) {
+ /* Don't mess with modes we don't support */
+ if (mode->first_lane > mode->last_lane)
+ serdes->used_lanes |=
+ GENMASK(mode->first_lane,
+ mode->last_lane);
+ else
+ serdes->used_lanes |=
+ GENMASK(mode->last_lane,
+ mode->first_lane);
+ if (grabbed_clocks)
+ continue;
+
+ grabbed_clocks = true;
+ clk_prepare_enable(serdes->clks[0].pll.clk);
+ clk_prepare_enable(serdes->clks[1].pll.clk);
+ clk_rate_exclusive_get(serdes->clks[0].pll.clk);
+ clk_rate_exclusive_get(serdes->clks[1].pll.clk);
+ } else {
+ /* Otherwise, clear out the existing config */
+ pccr = lynx_proto_mode_prep(mode, pccr,
+ LYNX_PROTO_NONE);
+ lynx_write(serdes, pccr, PCCRn(mode->pccr));
+ }
+
+ /* Disable the SGMII PCS until we're ready for it */
+ if (mode->protos & LYNX_PROTO_SGMII) {
+ u32 cr1;
+
+ cr1 = lynx_read(serdes, SGMIIaCR1(mode->idx));
+ cr1 &= ~SGMIIaCR1_SGPCS_EN;
+ lynx_write(serdes, cr1, SGMIIaCR1(mode->idx));
+ }
+ }
+ }
+
+ /* Power off non-used lanes */
+ for (i = 0; i < serdes->conf->lanes; i++) {
+ if (serdes->used_lanes & BIT(i))
+ continue;
+ lynx_power_off_lane(serdes, i);
+ }
+
+ ret = PTR_ERR_OR_ZERO(devm_of_phy_provider_register(dev, lynx_xlate));
+ if (ret)
+ dev_err_probe(dev, ret, "could not register phy provider\n");
+ else
+ dev_info(dev, "probed with %d lanes\n", serdes->conf->lanes);
+ return ret;
+}
+
+static const struct lynx_conf ls1046a_conf = {
+ .lanes = 4,
+ .caps = BIT(LYNX_HAS_1000BASEKX) | BIT(LYNX_HAS_10GKR),
+ .endian = REGMAP_ENDIAN_BIG,
+};
+
+static const struct lynx_conf ls1088a_conf = {
+ .lanes = 4,
+ .caps = BIT(LYNX_HAS_1000BASEKX) | BIT(LYNX_HAS_10GKR),
+ .endian = REGMAP_ENDIAN_LITTLE,
+};
+
+static const struct of_device_id lynx_of_match[] = {
+ { .compatible = "fsl,ls1046a-serdes", .data = &ls1046a_conf },
+ { .compatible = "fsl,ls1088a-serdes", .data = &ls1088a_conf },
+ { },
+};
+MODULE_DEVICE_TABLE(of, lynx_of_match);
+
+static struct platform_driver lynx_driver = {
+ .probe = lynx_probe,
+ .driver = {
+ .name = "lynx_10g",
+ .of_match_table = lynx_of_match,
+ },
+};
+module_platform_driver(lynx_driver);
+
+MODULE_AUTHOR("Sean Anderson <sean.anderson@seco.com>");
+MODULE_DESCRIPTION("Lynx 10G SerDes driver");
+MODULE_LICENSE("GPL");
--
2.35.1.1320.gc452695387.dirty
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH net-next v3 42/47] powerpc: dts: qoriq: Add nodes for QSGMII PCSs
2022-07-15 21:59 [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink Sean Anderson
` (3 preceding siblings ...)
2022-07-15 21:59 ` [PATCH net-next v3 06/47] [RFT] phy: fsl: Add Lynx 10G SerDes driver Sean Anderson
@ 2022-07-15 21:59 ` Sean Anderson
2022-07-21 13:48 ` Camelia Alexandra Groza
2022-07-15 21:59 ` [PATCH net-next v3 43/47] arm64: dts: layerscape: " Sean Anderson
` (5 subsequent siblings)
10 siblings, 1 reply; 30+ messages in thread
From: Sean Anderson @ 2022-07-15 21:59 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Madalin Bucur, netdev
Cc: Paolo Abeni, Eric Dumazet, linux-arm-kernel, Russell King,
linux-kernel, Sean Anderson, Benjamin Herrenschmidt,
Krzysztof Kozlowski, Li Yang, Michael Ellerman, Paul Mackerras,
Rob Herring, Shawn Guo, devicetree, linuxppc-dev
Now that we actually read registers from QSGMII PCSs, it's important
that we have the correct address (instead of hoping that we're the MAC
with all the QSGMII PCSs on its bus). This adds nodes for the QSGMII
PCSs. They have the same addresses on all SoCs (e.g. if QSGMIIA is
present it's used for MACs 1 through 4).
Since the first QSGMII PCSs share an address with the SGMII and XFI
PCSs, we only add new nodes for PCSs 2-4. This avoids address conflicts
on the bus.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---
Changes in v3:
- Add compatibles for QSGMII PCSs
- Split arm and powerpcs dts updates
Changes in v2:
- New
.../boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi | 3 ++-
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi | 10 +++++++++-
.../boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi | 10 +++++++++-
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi | 10 +++++++++-
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi | 3 ++-
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi | 10 +++++++++-
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi | 10 +++++++++-
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi | 10 +++++++++-
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi | 3 ++-
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi | 10 +++++++++-
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi | 10 +++++++++-
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi | 10 +++++++++-
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi | 3 ++-
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi | 10 +++++++++-
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi | 10 +++++++++-
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi | 10 +++++++++-
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi | 3 ++-
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi | 10 +++++++++-
18 files changed, 127 insertions(+), 18 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
index baa0c503e741..db169d630db3 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
@@ -55,7 +55,8 @@ ethernet@e0000 {
reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
ptp-timer = <&ptp_timer0>;
- pcsphy-handle = <&pcsphy0>;
+ pcsphy-handle = <&pcsphy0>, <&pcsphy0>;
+ pcs-names = "sgmii", "qsgmii";
};
mdio@e1000 {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
index 93095600e808..e80ad8675be8 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
@@ -52,7 +52,15 @@ ethernet@f0000 {
compatible = "fsl,fman-memac";
reg = <0xf0000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
- pcsphy-handle = <&pcsphy6>;
+ pcsphy-handle = <&pcsphy6>, <&qsgmiib_pcs2>, <&pcsphy6>;
+ pcs-names = "sgmii", "qsgmii", "xfi";
+ };
+
+ mdio@e9000 {
+ qsgmiib_pcs2: ethernet-pcs@2 {
+ compatible = "fsl,lynx-pcs";
+ reg = <2>;
+ };
};
mdio@f1000 {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
index ff4bd38f0645..6a6f51842ad5 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
@@ -55,7 +55,15 @@ ethernet@e2000 {
reg = <0xe2000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
ptp-timer = <&ptp_timer0>;
- pcsphy-handle = <&pcsphy1>;
+ pcsphy-handle = <&pcsphy1>, <&qsgmiia_pcs1>;
+ pcs-names = "sgmii", "qsgmii";
+ };
+
+ mdio@e1000 {
+ qsgmiia_pcs1: ethernet-pcs@1 {
+ compatible = "fsl,lynx-pcs";
+ reg = <1>;
+ };
};
mdio@e3000 {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
index 1fa38ed6f59e..543da5493e40 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
@@ -52,7 +52,15 @@ ethernet@f2000 {
compatible = "fsl,fman-memac";
reg = <0xf2000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
- pcsphy-handle = <&pcsphy7>;
+ pcsphy-handle = <&pcsphy7>, <&qsgmiib_pcs3>, <&pcsphy7>;
+ pcs-names = "sgmii", "qsgmii", "xfi";
+ };
+
+ mdio@e9000 {
+ qsgmiib_pcs3: ethernet-pcs@3 {
+ compatible = "fsl,lynx-pcs";
+ reg = <3>;
+ };
};
mdio@f3000 {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi
index a8cc9780c0c4..ce76725e6eb2 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi
@@ -51,7 +51,8 @@ ethernet@e0000 {
reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
ptp-timer = <&ptp_timer0>;
- pcsphy-handle = <&pcsphy0>;
+ pcsphy-handle = <&pcsphy0>, <&pcsphy0>;
+ pcs-names = "sgmii", "qsgmii";
};
mdio@e1000 {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi
index 8b8bd70c9382..f3af67df4767 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi
@@ -51,7 +51,15 @@ ethernet@e2000 {
reg = <0xe2000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
ptp-timer = <&ptp_timer0>;
- pcsphy-handle = <&pcsphy1>;
+ pcsphy-handle = <&pcsphy1>, <&qsgmiia_pcs1>;
+ pcs-names = "sgmii", "qsgmii";
+ };
+
+ mdio@e1000 {
+ qsgmiia_pcs1: ethernet-pcs@1 {
+ compatible = "fsl,lynx-pcs";
+ reg = <1>;
+ };
};
mdio@e3000 {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi
index 619c880b54d8..f6d74de84bfe 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi
@@ -51,7 +51,15 @@ ethernet@e4000 {
reg = <0xe4000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
ptp-timer = <&ptp_timer0>;
- pcsphy-handle = <&pcsphy2>;
+ pcsphy-handle = <&pcsphy2>, <&qsgmiia_pcs2>;
+ pcs-names = "sgmii", "qsgmii";
+ };
+
+ mdio@e1000 {
+ qsgmiia_pcs2: ethernet-pcs@2 {
+ compatible = "fsl,lynx-pcs";
+ reg = <2>;
+ };
};
mdio@e5000 {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi
index d7ebb73a400d..6e091d8ae9e2 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi
@@ -51,7 +51,15 @@ ethernet@e6000 {
reg = <0xe6000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
ptp-timer = <&ptp_timer0>;
- pcsphy-handle = <&pcsphy3>;
+ pcsphy-handle = <&pcsphy3>, <&qsgmiia_pcs3>;
+ pcs-names = "sgmii", "qsgmii";
+ };
+
+ mdio@e1000 {
+ qsgmiia_pcs3: ethernet-pcs@3 {
+ compatible = "fsl,lynx-pcs";
+ reg = <3>;
+ };
};
mdio@e7000 {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi
index b151d696a069..e2174c0fc841 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi
@@ -51,7 +51,8 @@ ethernet@e8000 {
reg = <0xe8000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
ptp-timer = <&ptp_timer0>;
- pcsphy-handle = <&pcsphy4>;
+ pcsphy-handle = <&pcsphy4>, <&pcsphy4>;
+ pcs-names = "sgmii", "qsgmii";
};
mdio@e9000 {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi
index adc0ae0013a3..9106815bd63e 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi
@@ -51,7 +51,15 @@ ethernet@ea000 {
reg = <0xea000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
ptp-timer = <&ptp_timer0>;
- pcsphy-handle = <&pcsphy5>;
+ pcsphy-handle = <&pcsphy5>, <&qsgmiib_pcs1>;
+ pcs-names = "sgmii", "qsgmii";
+ };
+
+ mdio@e9000 {
+ qsgmiib_pcs1: ethernet-pcs@1 {
+ compatible = "fsl,lynx-pcs";
+ reg = <1>;
+ };
};
mdio@eb000 {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi
index 435047e0e250..a3c1538dfda1 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi
@@ -52,7 +52,15 @@ ethernet@f0000 {
compatible = "fsl,fman-memac";
reg = <0xf0000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
- pcsphy-handle = <&pcsphy14>;
+ pcsphy-handle = <&pcsphy14>, <&qsgmiid_pcs2>, <&pcsphy14>;
+ pcs-names = "sgmii", "qsgmii", "xfi";
+ };
+
+ mdio@e9000 {
+ qsgmiid_pcs2: ethernet-pcs@2 {
+ compatible = "fsl,lynx-pcs";
+ reg = <2>;
+ };
};
mdio@f1000 {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi
index c098657cca0a..c024517e70d6 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi
@@ -52,7 +52,15 @@ ethernet@f2000 {
compatible = "fsl,fman-memac";
reg = <0xf2000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x11 &fman1_tx_0x31>;
- pcsphy-handle = <&pcsphy15>;
+ pcsphy-handle = <&pcsphy15>, <&qsgmiid_pcs3>, <&pcsphy15>;
+ pcs-names = "sgmii", "qsgmii", "xfi";
+ };
+
+ mdio@e9000 {
+ qsgmiid_pcs3: ethernet-pcs@3 {
+ compatible = "fsl,lynx-pcs";
+ reg = <3>;
+ };
};
mdio@f3000 {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi
index 9d06824815f3..16fb299f615a 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi
@@ -51,7 +51,8 @@ ethernet@e0000 {
reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x08 &fman1_tx_0x28>;
ptp-timer = <&ptp_timer1>;
- pcsphy-handle = <&pcsphy8>;
+ pcsphy-handle = <&pcsphy8>, <&pcsphy8>;
+ pcs-names = "sgmii", "qsgmii";
};
mdio@e1000 {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi
index 70e947730c4b..75cecbef8469 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi
@@ -51,7 +51,15 @@ ethernet@e2000 {
reg = <0xe2000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x09 &fman1_tx_0x29>;
ptp-timer = <&ptp_timer1>;
- pcsphy-handle = <&pcsphy9>;
+ pcsphy-handle = <&pcsphy9>, <&qsgmiic_pcs1>;
+ pcs-names = "sgmii", "qsgmii";
+ };
+
+ mdio@e1000 {
+ qsgmiic_pcs1: ethernet-pcs@1 {
+ compatible = "fsl,lynx-pcs";
+ reg = <1>;
+ };
};
mdio@e3000 {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi
index ad96e6529595..98c1d27f17e7 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi
@@ -51,7 +51,15 @@ ethernet@e4000 {
reg = <0xe4000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x0a &fman1_tx_0x2a>;
ptp-timer = <&ptp_timer1>;
- pcsphy-handle = <&pcsphy10>;
+ pcsphy-handle = <&pcsphy10>, <&qsgmiic_pcs2>;
+ pcs-names = "sgmii", "qsgmii";
+ };
+
+ mdio@e1000 {
+ qsgmiic_pcs2: ethernet-pcs@2 {
+ compatible = "fsl,lynx-pcs";
+ reg = <2>;
+ };
};
mdio@e5000 {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi
index 034bc4b71f7a..203a00036f17 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi
@@ -51,7 +51,15 @@ ethernet@e6000 {
reg = <0xe6000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x0b &fman1_tx_0x2b>;
ptp-timer = <&ptp_timer1>;
- pcsphy-handle = <&pcsphy11>;
+ pcsphy-handle = <&pcsphy11>, <&qsgmiic_pcs3>;
+ pcs-names = "sgmii", "qsgmii";
+ };
+
+ mdio@e1000 {
+ qsgmiic_pcs3: ethernet-pcs@3 {
+ compatible = "fsl,lynx-pcs";
+ reg = <3>;
+ };
};
mdio@e7000 {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi
index 93ca23d82b39..9366935ebc02 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi
@@ -51,7 +51,8 @@ ethernet@e8000 {
reg = <0xe8000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x0c &fman1_tx_0x2c>;
ptp-timer = <&ptp_timer1>;
- pcsphy-handle = <&pcsphy12>;
+ pcsphy-handle = <&pcsphy12>, <&pcsphy12>;
+ pcs-names = "sgmii", "qsgmii";
};
mdio@e9000 {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi
index 23b3117a2fd2..39f7c6133017 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi
@@ -51,7 +51,15 @@ ethernet@ea000 {
reg = <0xea000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x0d &fman1_tx_0x2d>;
ptp-timer = <&ptp_timer1>;
- pcsphy-handle = <&pcsphy13>;
+ pcsphy-handle = <&pcsphy13>, <&qsgmiid_pcs1>;
+ pcs-names = "sgmii", "qsgmii";
+ };
+
+ mdio@e9000 {
+ qsgmiid_pcs1: ethernet-pcs@1 {
+ compatible = "fsl,lynx-pcs";
+ reg = <1>;
+ };
};
mdio@eb000 {
--
2.35.1.1320.gc452695387.dirty
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH net-next v3 43/47] arm64: dts: layerscape: Add nodes for QSGMII PCSs
2022-07-15 21:59 [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink Sean Anderson
` (4 preceding siblings ...)
2022-07-15 21:59 ` [PATCH net-next v3 42/47] powerpc: dts: qoriq: Add nodes for QSGMII PCSs Sean Anderson
@ 2022-07-15 21:59 ` Sean Anderson
2022-07-15 21:59 ` [PATCH net-next v3 44/47] arm64: dts: ls1046a: Add serdes bindings Sean Anderson
` (4 subsequent siblings)
10 siblings, 0 replies; 30+ messages in thread
From: Sean Anderson @ 2022-07-15 21:59 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Madalin Bucur, netdev
Cc: Paolo Abeni, Eric Dumazet, linux-arm-kernel, Russell King,
linux-kernel, Sean Anderson, Benjamin Herrenschmidt,
Krzysztof Kozlowski, Li Yang, Michael Ellerman, Paul Mackerras,
Rob Herring, Shawn Guo, devicetree, linuxppc-dev
Now that we actually read registers from QSGMII PCSs, it's important
that we have the correct address (instead of hoping that we're the MAC
with all the QSGMII PCSs on its bus). This adds nodes for the QSGMII
PCSs. The exact mapping of QSGMII to MACs depends on the SoC.
Since the first QSGMII PCSs share an address with the SGMII and XFI
PCSs, we only add new nodes for PCSs 2-4. This avoids address conflicts
on the bus.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---
Changes in v3:
- Split this patch off from the previous one
Changes in v2:
- New
.../boot/dts/freescale/fsl-ls1043-post.dtsi | 24 ++++++++++++++++++
.../boot/dts/freescale/fsl-ls1046-post.dtsi | 25 +++++++++++++++++++
2 files changed, 49 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
index d237162a8744..02c51690b9da 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
@@ -24,9 +24,12 @@ &fman0 {
/* these aliases provide the FMan ports mapping */
enet0: ethernet@e0000 {
+ pcs-names = "qsgmii";
};
enet1: ethernet@e2000 {
+ pcsphy-handle = <&pcsphy1>, <&qsgmiib_pcs1>;
+ pcs-names = "sgmii", "qsgmii";
};
enet2: ethernet@e4000 {
@@ -36,11 +39,32 @@ enet3: ethernet@e6000 {
};
enet4: ethernet@e8000 {
+ pcsphy-handle = <&pcsphy4>, <&qsgmiib_pcs2>;
+ pcs-names = "sgmii", "qsgmii";
};
enet5: ethernet@ea000 {
+ pcsphy-handle = <&pcsphy5>, <&qsgmiib_pcs3>;
+ pcs-names = "sgmii", "qsgmii";
};
enet6: ethernet@f0000 {
};
+
+ mdio@e1000 {
+ qsgmiib_pcs1: ethernet-pcs@1 {
+ compatible = "fsl,lynx-pcs";
+ reg = <0x1>;
+ };
+
+ qsgmiib_pcs2: ethernet-pcs@2 {
+ compatible = "fsl,lynx-pcs";
+ reg = <0x2>;
+ };
+
+ qsgmiib_pcs3: ethernet-pcs@3 {
+ compatible = "fsl,lynx-pcs";
+ reg = <0x3>;
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
index d6caaea57d90..1ce40c35f344 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
@@ -23,6 +23,8 @@ &soc {
&fman0 {
/* these aliases provide the FMan ports mapping */
enet0: ethernet@e0000 {
+ pcsphy-handle = <&qsgmiib_pcs3>;
+ pcs-names = "qsgmii";
};
enet1: ethernet@e2000 {
@@ -35,14 +37,37 @@ enet3: ethernet@e6000 {
};
enet4: ethernet@e8000 {
+ pcsphy-handle = <&pcsphy4>, <&qsgmiib_pcs1>;
+ pcs-names = "sgmii", "qsgmii";
};
enet5: ethernet@ea000 {
+ pcsphy-handle = <&pcsphy5>, <&pcsphy5>;
+ pcs-names = "sgmii", "qsgmii";
};
enet6: ethernet@f0000 {
};
enet7: ethernet@f2000 {
+ pcsphy-handle = <&pcsphy7>, <&qsgmiib_pcs2>, <&pcsphy7>;
+ pcs-names = "sgmii", "qsgmii", "xfi";
+ };
+
+ mdio@eb000 {
+ qsgmiib_pcs1: ethernet-pcs@1 {
+ compatible = "fsl,lynx-pcs";
+ reg = <0x1>;
+ };
+
+ qsgmiib_pcs2: ethernet-pcs@2 {
+ compatible = "fsl,lynx-pcs";
+ reg = <0x2>;
+ };
+
+ qsgmiib_pcs3: ethernet-pcs@3 {
+ compatible = "fsl,lynx-pcs";
+ reg = <0x3>;
+ };
};
};
--
2.35.1.1320.gc452695387.dirty
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH net-next v3 44/47] arm64: dts: ls1046a: Add serdes bindings
2022-07-15 21:59 [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink Sean Anderson
` (5 preceding siblings ...)
2022-07-15 21:59 ` [PATCH net-next v3 43/47] arm64: dts: layerscape: " Sean Anderson
@ 2022-07-15 21:59 ` Sean Anderson
2022-07-15 21:59 ` [PATCH net-next v3 45/47] arm64: dts: ls1088a: " Sean Anderson
` (3 subsequent siblings)
10 siblings, 0 replies; 30+ messages in thread
From: Sean Anderson @ 2022-07-15 21:59 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Madalin Bucur, netdev
Cc: Paolo Abeni, Eric Dumazet, linux-arm-kernel, Russell King,
linux-kernel, Sean Anderson, Krzysztof Kozlowski, Li Yang,
Rob Herring, Shawn Guo, devicetree
This adds bindings for the SerDes devices. They are disabled by default
to prevent any breakage on existing boards.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---
Changes in v3:
- Describe modes in device tree
Changes in v2:
- Use one phy cell for SerDes1, since no lanes can be grouped
- Disable SerDes by default to prevent breaking boards inadvertently.
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 179 ++++++++++++++++++
1 file changed, 179 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 0085e83adf65..0b3765cad383 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -413,6 +413,185 @@ bportals: bman-portals@508000000 {
ranges = <0x0 0x5 0x08000000 0x8000000>;
};
+ /*
+ * XXX: For SerDes1, lane A uses pins SD1_RX3_P/N! That is, the
+ * lane numbers and pin numbers are _reversed_. In addition,
+ * the PCCR documentation is _inconsistent_ in its usage of
+ * these terms!
+ *
+ * PCCR "Lane 0" refers to...
+ * ==== =====================
+ * 0 Lane A
+ * 2 Lane A
+ * 8 Lane A
+ * 9 Lane A
+ * B Lane D!
+ */
+ serdes1: phy@1ea0000 {
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+ compatible = "fsl,ls1046a-serdes", "fsl,lynx-10g";
+ reg = <0x0 0x1ea0000 0x0 0x2000>;
+ status = "disabled";
+
+ pccr-0 {
+ fsl,pccr = <0x0>;
+
+ /* PCIe.1 x1 */
+ pcie-0 {
+ fsl,index = <0>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <1>;
+ fsl,proto = "pcie";
+ };
+ };
+
+ pccr-8 {
+ fsl,pccr = <0x8>;
+
+ /* SGMII.6 */
+ sgmii-0 {
+ fsl,index = <0>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <0>;
+ fsl,proto = "sgmii";
+ };
+
+ /* SGMII.5 */
+ sgmii-1 {
+ fsl,index = <1>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <1>;
+ fsl,proto = "sgmii25";
+ };
+
+ /* SGMII.10 */
+ sgmii-2 {
+ fsl,index = <2>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <2>;
+ fsl,proto = "sgmii25";
+ };
+
+ /* SGMII.9 */
+ sgmii-3 {
+ fsl,index = <3>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <3>;
+ fsl,proto = "sgmii25";
+ };
+ };
+
+ pccr-9 {
+ fsl,pccr = <0x9>;
+
+ /* QSGMII.6,5,10,1 */
+ qsgmii-1 {
+ fsl,index = <1>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <1>;
+ fsl,proto = "qsgmii";
+ };
+ };
+
+ pccr-b {
+ fsl,pccr = <0xb>;
+
+ /* XFI.10 */
+ xfi-0 {
+ fsl,index = <0>;
+ fsl,cfg = <0x2>;
+ fsl,first-lane = <2>;
+ fsl,proto = "xfi";
+ };
+
+ /* XFI.9 */
+ xfi-1 {
+ fsl,index = <1>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <3>;
+ fsl,proto = "xfi";
+ };
+ };
+ };
+
+ serdes2: phy@1eb0000 {
+ #clock-cells = <1>;
+ #phy-cells = <2>;
+ compatible = "fsl,ls1046a-serdes", "fsl,lynx-10g";
+ reg = <0x0 0x1eb0000 0x0 0x2000>;
+ status = "disabled";
+
+ pccr-0 {
+ fsl,pccr = <0>;
+
+ pcie-0 {
+ fsl,index = <0>;
+ fsl,proto = "pcie";
+
+ /* PCIe.1 x1 */
+ cfg-1 {
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <1>;
+ };
+
+ /* PCIe.1 x4 */
+ cfg-3 {
+ fsl,cfg = <0x3>;
+ fsl,first-lane = <0>;
+ fsl,last-lane = <3>;
+ };
+ };
+
+ pcie-2 {
+ fsl,index = <2>;
+ fsl,proto = "pcie";
+
+ /* PCIe.2 x1 */
+ cfg-1 {
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <2>;
+ };
+
+ /* PCIe.3 x2 */
+ cfg-2 {
+ fsl,cfg = <0x2>;
+ fsl,first-lane = <2>;
+ fsl,last-lane = <3>;
+ };
+
+ /* PCIe.3 x1 */
+ cfg-3 {
+ fsl,cfg = <0x3>;
+ fsl,first-lane = <3>;
+ };
+ };
+ };
+
+ pccr-2 {
+ fsl,pccr = <0x2>;
+
+ sata-0 {
+ fsl,index = <0>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <3>;
+ fsl,proto = "sata";
+ };
+ };
+
+ pccr-8 {
+ fsl,pccr = <0x8>;
+
+ /* SGMII.2 */
+ sgmii-1 {
+ fsl,index = <1>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <1>;
+ fsl,proto = "sgmii";
+ };
+ };
+ };
+
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1046a-dcfg", "syscon";
reg = <0x0 0x1ee0000 0x0 0x1000>;
--
2.35.1.1320.gc452695387.dirty
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH net-next v3 45/47] arm64: dts: ls1088a: Add serdes bindings
2022-07-15 21:59 [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink Sean Anderson
` (6 preceding siblings ...)
2022-07-15 21:59 ` [PATCH net-next v3 44/47] arm64: dts: ls1046a: Add serdes bindings Sean Anderson
@ 2022-07-15 21:59 ` Sean Anderson
2022-07-15 21:59 ` [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: " Sean Anderson
` (2 subsequent siblings)
10 siblings, 0 replies; 30+ messages in thread
From: Sean Anderson @ 2022-07-15 21:59 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Madalin Bucur, netdev
Cc: Paolo Abeni, Eric Dumazet, linux-arm-kernel, Russell King,
linux-kernel, Sean Anderson, Krzysztof Kozlowski, Li Yang,
Rob Herring, Shawn Guo, devicetree
This adds bindings for the SerDes devices. They are disabled by default
to prevent any breakage on existing boards.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---
Changes in v3:
- New
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 96 +++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index f476b7d8b056..987892bc69d7 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -238,6 +238,102 @@ reset: syscon@1e60000 {
reg = <0x0 0x1e60000 0x0 0x10000>;
};
+ serdes1: phy@1ea0000 {
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+ compatible = "fsl,ls1088a-serdes", "fsl,lynx-10g";
+ reg = <0x0 0x1ea0000 0x0 0x2000>;
+ status = "disabled";
+
+ pccr-8 {
+ fsl,pccr = <0x8>;
+
+ /* SG3 */
+ sgmii-0 {
+ fsl,index = <0>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <3>;
+ fsl,proto = "sgmii";
+ };
+
+ /* SG7 */
+ sgmii-1 {
+ fsl,index = <1>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <2>;
+ fsl,proto = "sgmii";
+ };
+
+ /* SG1 */
+ sgmii-2 {
+ fsl,index = <2>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <1>;
+ fsl,proto = "sgmii25";
+ };
+
+ /* SG2 */
+ sgmii-3 {
+ fsl,index = <3>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <0>;
+ fsl,proto = "sgmii25";
+ };
+ };
+
+ pccr-9 {
+ fsl,pccr = <0x9>;
+
+ /* QSGa */
+ qsgmii-0 {
+ fsl,index = <0>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <3>;
+ fsl,proto = "qsgmii";
+ };
+
+ /* QSGb */
+ qsgmii-1 {
+ fsl,index = <1>;
+ fsl,proto = "qsgmii";
+
+ cfg-1 {
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <2>;
+ };
+
+ cfg-2 {
+ fsl,cfg = <0x2>;
+ fsl,first-lane = <0>;
+ };
+ };
+ };
+
+ pccr-b {
+ fsl,pccr = <0xb>;
+
+ /* XFI1 */
+ xfi-0 {
+ fsl,index = <0>;
+ fsl,cfg = <0x1>;
+ /*
+ * Table 23-1 and section 23.5.16.4
+ * disagree; this reflects the table
+ */
+ fsl,first-lane = <1>;
+ fsl,proto = "xfi";
+ };
+
+ /* XFI2 */
+ xfi-1 {
+ fsl,index = <1>;
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <0>;
+ fsl,proto = "xfi";
+ };
+ };
+ };
+
isc: syscon@1f70000 {
compatible = "fsl,ls1088a-isc", "syscon";
reg = <0x0 0x1f70000 0x0 0x10000>;
--
2.35.1.1320.gc452695387.dirty
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes bindings
2022-07-15 21:59 [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink Sean Anderson
` (7 preceding siblings ...)
2022-07-15 21:59 ` [PATCH net-next v3 45/47] arm64: dts: ls1088a: " Sean Anderson
@ 2022-07-15 21:59 ` Sean Anderson
2022-07-21 14:20 ` Camelia Alexandra Groza
2022-07-15 21:59 ` [PATCH net-next v3 47/47] [WIP] arm64: dts: ls1088ardb: " Sean Anderson
2022-07-21 14:26 ` [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink Camelia Alexandra Groza
10 siblings, 1 reply; 30+ messages in thread
From: Sean Anderson @ 2022-07-15 21:59 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Madalin Bucur, netdev
Cc: Paolo Abeni, Eric Dumazet, linux-arm-kernel, Russell King,
linux-kernel, Sean Anderson, Kishon Vijay Abraham I,
Krzysztof Kozlowski, Li Yang, Rob Herring, Shawn Guo, Vinod Koul,
devicetree, linux-phy
This adds appropriate bindings for the macs which use the SerDes. The
156.25MHz fixed clock is a crystal. The 100MHz clocks (there are
actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is
no driver for this device (and as far as I know all you can do with the
100MHz clocks is gate them), so I have chosen to model it as a single
fixed clock.
Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
This means that Lane A (what the driver thinks is lane 0) uses pins
SD1_TX3_P/N.
Because this will break ethernet if the serdes is not enabled, enable
the serdes driver by default on Layerscape.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---
Please let me know if there is a better/more specific config I can use
here.
(no changes since v1)
.../boot/dts/freescale/fsl-ls1046a-rdb.dts | 34 +++++++++++++++++++
drivers/phy/freescale/Kconfig | 1 +
2 files changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index 7025aad8ae89..4f4dd0ed8c53 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -26,6 +26,32 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ clocks {
+ clk_100mhz: clock-100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk_156mhz: clock-156mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <156250000>;
+ };
+ };
+};
+
+&serdes1 {
+ clocks = <&clk_100mhz>, <&clk_156mhz>;
+ clock-names = "ref0", "ref1";
+ status = "okay";
+};
+
+&serdes2 {
+ clocks = <&clk_100mhz>, <&clk_100mhz>;
+ clock-names = "ref0", "ref1";
+ status = "okay";
};
&duart0 {
@@ -140,21 +166,29 @@ ethernet@e6000 {
ethernet@e8000 {
phy-handle = <&sgmii_phy1>;
phy-connection-type = "sgmii";
+ phys = <&serdes1 1>;
+ phy-names = "serdes";
};
ethernet@ea000 {
phy-handle = <&sgmii_phy2>;
phy-connection-type = "sgmii";
+ phys = <&serdes1 0>;
+ phy-names = "serdes";
};
ethernet@f0000 { /* 10GEC1 */
phy-handle = <&aqr106_phy>;
phy-connection-type = "xgmii";
+ phys = <&serdes1 3>;
+ phy-names = "serdes";
};
ethernet@f2000 { /* 10GEC2 */
fixed-link = <0 1 1000 0 0>;
phy-connection-type = "xgmii";
+ phys = <&serdes1 2>;
+ phy-names = "serdes";
};
mdio@fc000 {
diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
index fe2a3efe0ba4..9595666213d0 100644
--- a/drivers/phy/freescale/Kconfig
+++ b/drivers/phy/freescale/Kconfig
@@ -43,6 +43,7 @@ config PHY_FSL_LYNX_10G
tristate "Freescale Layerscale Lynx 10G SerDes support"
select GENERIC_PHY
select REGMAP_MMIO
+ default y if ARCH_LAYERSCAPE
help
This adds support for the Lynx "SerDes" devices found on various QorIQ
SoCs. There may be up to four SerDes devices on each SoC, and each
--
2.35.1.1320.gc452695387.dirty
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH net-next v3 47/47] [WIP] arm64: dts: ls1088ardb: Add serdes bindings
2022-07-15 21:59 [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink Sean Anderson
` (8 preceding siblings ...)
2022-07-15 21:59 ` [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: " Sean Anderson
@ 2022-07-15 21:59 ` Sean Anderson
2022-07-21 14:26 ` [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink Camelia Alexandra Groza
10 siblings, 0 replies; 30+ messages in thread
From: Sean Anderson @ 2022-07-15 21:59 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Madalin Bucur, netdev
Cc: Paolo Abeni, Eric Dumazet, linux-arm-kernel, Russell King,
linux-kernel, Sean Anderson, Ioana Ciornei,
Kishon Vijay Abraham I, Krzysztof Kozlowski, Li Yang, Rob Herring,
Shawn Guo, Vinod Koul, devicetree, linux-phy
This is a first stab at adding serdes support on the LS1088A. Linux hangs
around when the serdes is initialized if the si5341 is enabled, so it's
commented out. I also discovered that I have too old MC firmware to
reconfigure the phy interface mode. Consider all the LS1088A parts of
this series to be untested, but hopefully they can be a good starting
point.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---
(no changes since v1)
.../boot/dts/freescale/fsl-ls1088a-rdb.dts | 87 +++++++++++++++++++
1 file changed, 87 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
index 1bfbce69cc8b..5875709f7f8b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -15,12 +15,59 @@
/ {
model = "LS1088A RDB Board";
compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
+
+ clocks {
+ si5341_xtal: clock-48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ clk_100mhz: clock-100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk_156mhz: clock-156mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <156250000>;
+ };
+ };
+
+ ovdd: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "ovdd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ dvdd: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "dvdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+};
+
+&serdes1 {
+ //clocks = <&si5341 0 8>, <&si5341 0 9>;
+ clocks = <&clk_100mhz>, <&clk_156mhz>;
+ clock-names = "ref0", "ref1";
+ status = "okay";
+};
+
+&dpmac1 {
+ phys = <&serdes1 1>;
};
&dpmac2 {
phy-handle = <&mdio2_aquantia_phy>;
phy-connection-type = "10gbase-r";
pcs-handle = <&pcs2>;
+ phys = <&serdes1 0>;
};
&dpmac3 {
@@ -28,6 +75,7 @@ &dpmac3 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_0>;
+ phys = <&serdes1 3>;
};
&dpmac4 {
@@ -35,6 +83,7 @@ &dpmac4 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_1>;
+ phys = <&serdes1 3>;
};
&dpmac5 {
@@ -42,6 +91,7 @@ &dpmac5 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_2>;
+ phys = <&serdes1 3>;
};
&dpmac6 {
@@ -49,6 +99,7 @@ &dpmac6 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_3>;
+ phys = <&serdes1 3>;
};
&dpmac7 {
@@ -56,6 +107,7 @@ &dpmac7 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs7_0>;
+ phys = <&serdes1 2>;
};
&dpmac8 {
@@ -63,6 +115,7 @@ &dpmac8 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs7_1>;
+ phys = <&serdes1 2>;
};
&dpmac9 {
@@ -70,6 +123,7 @@ &dpmac9 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs7_2>;
+ phys = <&serdes1 2>;
};
&dpmac10 {
@@ -77,6 +131,7 @@ &dpmac10 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs7_3>;
+ phys = <&serdes1 2>;
};
&emdio1 {
@@ -142,6 +197,38 @@ i2c-switch@77 {
#address-cells = <1>;
#size-cells = <0>;
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+
+ si5341: clock-generator@74 {
+ #address-cells = <1>;
+ #clock-cells = <2>;
+ #size-cells = <0>;
+ compatible = "silabs,si5341";
+ reg = <0x74>;
+ clocks = <&si5341_xtal>;
+ clock-names = "xtal";
+ vdd-supply = <&ovdd>;
+ vdda-supply = <&dvdd>;
+ vddo8-supply = <&ovdd>;
+ vddo9-supply = <&ovdd>;
+ silabs,iovdd-33;
+ status = "disabled";
+
+ out@8 {
+ reg = <8>;
+ silabs,format = <1>;
+ };
+
+ out@9 {
+ reg = <9>;
+ silabs,format = <1>;
+ };
+ };
+ };
+
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
--
2.35.1.1320.gc452695387.dirty
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH net-next v3 03/47] dt-bindings: net: Convert FMan MAC bindings to yaml
2022-07-15 21:59 ` [PATCH net-next v3 03/47] dt-bindings: net: Convert FMan MAC bindings to yaml Sean Anderson
@ 2022-07-15 23:06 ` Rob Herring
2022-07-16 22:47 ` Sean Anderson
0 siblings, 1 reply; 30+ messages in thread
From: Rob Herring @ 2022-07-15 23:06 UTC (permalink / raw)
To: Sean Anderson
Cc: devicetree, Rob Herring, Russell King, netdev, Paolo Abeni,
Madalin Bucur, Eric Dumazet, David S . Miller,
Krzysztof Kozlowski, Jakub Kicinski, linux-arm-kernel,
linux-kernel
On Fri, 15 Jul 2022 17:59:10 -0400, Sean Anderson wrote:
> This converts the MAC portion of the FMan MAC bindings to yaml.
>
> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
>
> Changes in v3:
> - Incorperate some minor changes into the first FMan binding commit
>
> Changes in v2:
> - New
>
> .../bindings/net/fsl,fman-dtsec.yaml | 145 ++++++++++++++++++
> .../devicetree/bindings/net/fsl-fman.txt | 128 +---------------
> 2 files changed, 146 insertions(+), 127 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/fsl,fman-dtsec.example.dtb: ethernet@e8000: 'phy-connection-type', 'phy-handle' do not match any of the regexes: 'pinctrl-[0-9]+'
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH net-next v3 06/47] [RFT] phy: fsl: Add Lynx 10G SerDes driver
2022-07-15 21:59 ` [PATCH net-next v3 06/47] [RFT] phy: fsl: Add Lynx 10G SerDes driver Sean Anderson
@ 2022-07-16 22:39 ` kernel test robot
0 siblings, 0 replies; 30+ messages in thread
From: kernel test robot @ 2022-07-16 22:39 UTC (permalink / raw)
To: Sean Anderson, David S . Miller, Jakub Kicinski, Madalin Bucur,
netdev
Cc: kbuild-all, Paolo Abeni, Eric Dumazet, linux-arm-kernel,
Russell King, linux-kernel, Sean Anderson, Ioana Ciornei,
Jonathan Corbet, Kishon Vijay Abraham I, Krzysztof Kozlowski,
Rob Herring, Vinod Koul, devicetree, linux-doc, linux-phy
Hi Sean,
I love your patch! Yet something to improve:
[auto build test ERROR on net-next/master]
url: https://github.com/intel-lab-lkp/linux/commits/Sean-Anderson/net-dpaa-Convert-to-phylink/20220717-002036
base: https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git 2acd1022549e210edc4cfc9fc65b07b88751f0d9
config: i386-allyesconfig (https://download.01.org/0day-ci/archive/20220717/202207170654.0sfLE3ua-lkp@intel.com/config)
compiler: gcc-11 (Debian 11.3.0-3) 11.3.0
reproduce (this is a W=1 build):
# https://github.com/intel-lab-lkp/linux/commit/fbc22d79121541a0f957e0c209810c37570041b5
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Sean-Anderson/net-dpaa-Convert-to-phylink/20220717-002036
git checkout fbc22d79121541a0f957e0c209810c37570041b5
# save the config file
mkdir build_dir && cp config build_dir/.config
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/phy/freescale/phy-fsl-lynx-10g-clk.c: In function 'lynx_pll_recalc_rate':
>> drivers/phy/freescale/phy-fsl-lynx-10g-clk.c:211:25: error: implicit declaration of function 'FIELD_GET' [-Werror=implicit-function-declaration]
211 | u32 frate_sel = FIELD_GET(PLLaCR0_FRATE_SEL, cr0);
| ^~~~~~~~~
drivers/phy/freescale/phy-fsl-lynx-10g-clk.c: In function 'lynx_pll_set_rate':
>> drivers/phy/freescale/phy-fsl-lynx-10g-clk.c:294:16: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]
294 | cr0 |= FIELD_PREP(PLLaCR0_RFCLK_SEL, rfclk_sel);
| ^~~~~~~~~~
drivers/phy/freescale/phy-fsl-lynx-10g-clk.c: In function 'lynx_clk_init':
>> drivers/phy/freescale/phy-fsl-lynx-10g-clk.c:404:9: error: implicit declaration of function 'kfree'; did you mean 'vfree'? [-Werror=implicit-function-declaration]
404 | kfree(ref_name);
| ^~~~~
| vfree
cc1: some warnings being treated as errors
vim +/FIELD_GET +211 drivers/phy/freescale/phy-fsl-lynx-10g-clk.c
205
206 static unsigned long lynx_pll_recalc_rate(struct clk_hw *hw,
207 unsigned long parent_rate)
208 {
209 struct lynx_clk *clk = lynx_pll_to_clk(hw);
210 u32 cr0 = lynx_read(clk, PLLaCR0(clk->idx));
> 211 u32 frate_sel = FIELD_GET(PLLaCR0_FRATE_SEL, cr0);
212 u32 rfclk_sel = FIELD_GET(PLLaCR0_RFCLK_SEL, cr0);
213 unsigned long ret;
214
215 dev_dbg(clk->dev, "%s(pll%d, %lu)\n", __func__,
216 clk->idx, parent_rate);
217
218 ret = mult_frac(parent_rate, lynx_pll_ratio(frate_sel, rfclk_sel),
219 HZ_PER_KHZ);
220 return ret;
221 }
222
223 static long lynx_pll_round_rate(struct clk_hw *hw, unsigned long rate_khz,
224 unsigned long *parent_rate)
225 {
226 int frate_sel, rfclk_sel;
227 struct lynx_clk *clk = lynx_pll_to_clk(hw);
228 u32 ratio;
229
230 dev_dbg(clk->dev, "%s(pll%d, %lu, %lu)\n", __func__,
231 clk->idx, rate_khz, *parent_rate);
232
233 frate_sel = lynx_frate_to_sel(rate_khz);
234 if (frate_sel < 0)
235 return frate_sel;
236
237 rfclk_sel = lynx_rfclk_to_sel(*parent_rate);
238 if (rfclk_sel >= 0) {
239 ratio = lynx_pll_ratio(frate_sel, rfclk_sel);
240 if (ratio)
241 return mult_frac(*parent_rate, ratio, HZ_PER_KHZ);
242 }
243
244 for (rfclk_sel = 0;
245 rfclk_sel < ARRAY_SIZE(rfclk_sel_map);
246 rfclk_sel++) {
247 ratio = lynx_pll_ratio(frate_sel, rfclk_sel);
248 if (ratio) {
249 *parent_rate = rfclk_sel_map[rfclk_sel];
250 return mult_frac(*parent_rate, ratio, HZ_PER_KHZ);
251 }
252 }
253
254 return -EINVAL;
255 }
256
257 static int lynx_pll_set_rate(struct clk_hw *hw, unsigned long rate_khz,
258 unsigned long parent_rate)
259 {
260 int frate_sel, rfclk_sel, ret;
261 struct lynx_clk *clk = lynx_pll_to_clk(hw);
262 u32 ratio, cr0 = lynx_read(clk, PLLaCR0(clk->idx));
263
264 dev_dbg(clk->dev, "%s(pll%d, %lu, %lu)\n", __func__,
265 clk->idx, rate_khz, parent_rate);
266
267 frate_sel = lynx_frate_to_sel(rate_khz);
268 if (frate_sel < 0)
269 return frate_sel;
270
271 /* First try the existing rate */
272 rfclk_sel = lynx_rfclk_to_sel(parent_rate);
273 if (rfclk_sel >= 0) {
274 ratio = lynx_pll_ratio(frate_sel, rfclk_sel);
275 if (ratio)
276 goto got_rfclk;
277 }
278
279 for (rfclk_sel = 0;
280 rfclk_sel < ARRAY_SIZE(rfclk_sel_map);
281 rfclk_sel++) {
282 ratio = lynx_pll_ratio(frate_sel, rfclk_sel);
283 if (ratio) {
284 ret = clk_set_rate(clk->ref, rfclk_sel_map[rfclk_sel]);
285 if (!ret)
286 goto got_rfclk;
287 }
288 }
289
290 return ret;
291
292 got_rfclk:
293 cr0 &= ~(PLLaCR0_RFCLK_SEL | PLLaCR0_FRATE_SEL);
> 294 cr0 |= FIELD_PREP(PLLaCR0_RFCLK_SEL, rfclk_sel);
295 cr0 |= FIELD_PREP(PLLaCR0_FRATE_SEL, frate_sel);
296 lynx_write(clk, cr0, PLLaCR0(clk->idx));
297 return 0;
298 }
299
300 static const struct clk_ops lynx_pll_clk_ops = {
301 .prepare = lynx_pll_prepare,
302 .disable = lynx_pll_disable,
303 .is_enabled = lynx_pll_is_enabled,
304 .recalc_rate = lynx_pll_recalc_rate,
305 .round_rate = lynx_pll_round_rate,
306 .set_rate = lynx_pll_set_rate,
307 };
308
309 static void lynx_ex_dly_disable(struct clk_hw *hw)
310 {
311 struct lynx_clk *clk = lynx_ex_dly_to_clk(hw);
312 u32 cr0 = lynx_read(clk, PLLaCR0(clk->idx));
313
314 cr0 &= ~PLLaCR0_DLYDIV_SEL;
315 lynx_write(clk, PLLaCR0(clk->idx), cr0);
316 }
317
318 static int lynx_ex_dly_enable(struct clk_hw *hw)
319 {
320 struct lynx_clk *clk = lynx_ex_dly_to_clk(hw);
321 u32 cr0 = lynx_read(clk, PLLaCR0(clk->idx));
322
323 cr0 &= ~PLLaCR0_DLYDIV_SEL;
324 cr0 |= FIELD_PREP(PLLaCR0_DLYDIV_SEL, PLLaCR0_DLYDIV_SEL_16);
325 lynx_write(clk, PLLaCR0(clk->idx), cr0);
326 return 0;
327 }
328
329 static int lynx_ex_dly_is_enabled(struct clk_hw *hw)
330 {
331 struct lynx_clk *clk = lynx_ex_dly_to_clk(hw);
332
333 return lynx_read(clk, PLLaCR0(clk->idx)) & PLLaCR0_DLYDIV_SEL;
334 }
335
336 static unsigned long lynx_ex_dly_recalc_rate(struct clk_hw *hw,
337 unsigned long parent_rate)
338 {
339 return parent_rate / 16;
340 }
341
342 static const struct clk_ops lynx_ex_dly_clk_ops = {
343 .enable = lynx_ex_dly_enable,
344 .disable = lynx_ex_dly_disable,
345 .is_enabled = lynx_ex_dly_is_enabled,
346 .recalc_rate = lynx_ex_dly_recalc_rate,
347 };
348
349 static int lynx_clk_init(struct lynx_clk *clk, struct device *dev,
350 struct regmap *regmap, unsigned int index)
351 {
352 const struct clk_hw *pll_parents, *ex_dly_parents;
353 struct clk_init_data pll_init = {
354 .ops = &lynx_pll_clk_ops,
355 .parent_hws = &pll_parents,
356 .num_parents = 1,
357 .flags = CLK_SET_RATE_GATE | CLK_GET_RATE_NOCACHE |
358 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
359 };
360 struct clk_init_data ex_dly_init = {
361 .ops = &lynx_ex_dly_clk_ops,
362 .parent_hws = &ex_dly_parents,
363 .num_parents = 1,
364 };
365 char *ref_name;
366 int ret;
367
368 clk->dev = dev;
369 clk->regmap = regmap;
370 clk->idx = index;
371
372 ref_name = kasprintf(GFP_KERNEL, "ref%d", index);
373 pll_init.name = kasprintf(GFP_KERNEL, "%s.pll%d", dev_name(dev), index);
374 ex_dly_init.name = kasprintf(GFP_KERNEL, "%s_ex_dly", pll_init.name);
375 if (!ref_name || !pll_init.name || !ex_dly_init.name) {
376 ret = -ENOMEM;
377 goto out;
378 }
379
380 clk->ref = devm_clk_get(dev, ref_name);
381 if (IS_ERR(clk->ref)) {
382 ret = PTR_ERR(clk->ref);
383 dev_err_probe(dev, ret, "could not get %s\n", ref_name);
384 goto out;
385 }
386
387 pll_parents = __clk_get_hw(clk->ref);
388 clk->pll.init = &pll_init;
389 ret = devm_clk_hw_register(dev, &clk->pll);
390 if (ret) {
391 dev_err_probe(dev, ret, "could not register %s\n",
392 pll_init.name);
393 goto out;
394 }
395
396 ex_dly_parents = &clk->pll;
397 clk->ex_dly.init = &ex_dly_init;
398 ret = devm_clk_hw_register(dev, &clk->ex_dly);
399 if (ret)
400 dev_err_probe(dev, ret, "could not register %s\n",
401 ex_dly_init.name);
402
403 out:
> 404 kfree(ref_name);
405 kfree(pll_init.name);
406 kfree(ex_dly_init.name);
407 return ret;
408 }
409
--
0-DAY CI Kernel Test Service
https://01.org/lkp
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH net-next v3 03/47] dt-bindings: net: Convert FMan MAC bindings to yaml
2022-07-15 23:06 ` Rob Herring
@ 2022-07-16 22:47 ` Sean Anderson
2022-07-21 14:42 ` Krzysztof Kozlowski
0 siblings, 1 reply; 30+ messages in thread
From: Sean Anderson @ 2022-07-16 22:47 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, Rob Herring, Russell King, netdev, Paolo Abeni,
Madalin Bucur, Eric Dumazet, David S . Miller,
Krzysztof Kozlowski, Jakub Kicinski, linux-arm-kernel,
linux-kernel
On 7/15/22 7:06 PM, Rob Herring wrote:
> On Fri, 15 Jul 2022 17:59:10 -0400, Sean Anderson wrote:
>> This converts the MAC portion of the FMan MAC bindings to yaml.
>>
>> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> ---
>>
>> Changes in v3:
>> - Incorporate some minor changes into the first FMan binding commit
>>
>> Changes in v2:
>> - New
>>
>> .../bindings/net/fsl,fman-dtsec.yaml | 145 ++++++++++++++++++
>> .../devicetree/bindings/net/fsl-fman.txt | 128 +---------------
>> 2 files changed, 146 insertions(+), 127 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
>>
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/fsl,fman-dtsec.example.dtb: ethernet@e8000: 'phy-connection-type', 'phy-handle' do not match any of the regexes: 'pinctrl-[0-9]+'
> From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
>
> doc reference errors (make refcheckdocs):
What's the correct way to do this? I have '$ref: ethernet-controller.yaml#'
under allOf, but it doesn't seem to apply. IIRC this doesn't occur for actual dts files.
--Sean
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH net-next v3 01/47] dt-bindings: phy: Add Lynx 10G phy binding
2022-07-15 21:59 ` [PATCH net-next v3 01/47] dt-bindings: phy: Add Lynx 10G phy binding Sean Anderson
@ 2022-07-20 22:17 ` Rob Herring
2022-07-21 16:05 ` Sean Anderson
0 siblings, 1 reply; 30+ messages in thread
From: Rob Herring @ 2022-07-20 22:17 UTC (permalink / raw)
To: Sean Anderson
Cc: David S . Miller, Jakub Kicinski, Madalin Bucur, netdev,
Paolo Abeni, Eric Dumazet, linux-arm-kernel, Russell King,
linux-kernel, Kishon Vijay Abraham I, Krzysztof Kozlowski,
Vinod Koul, devicetree, linux-phy
On Fri, Jul 15, 2022 at 05:59:08PM -0400, Sean Anderson wrote:
> This adds a binding for the SerDes module found on QorIQ processors. The
> phy reference has two cells, one for the first lane and one for the
> last. This should allow for good support of multi-lane protocols when
> (if) they are added. There is no protocol option, because the driver is
> designed to be able to completely reconfigure lanes at runtime.
> Generally, the phy consumer can select the appropriate protocol using
> set_mode. For the most part there is only one protocol controller
> (consumer) per lane/protocol combination. The exception to this is the
> B4860 processor, which has some lanes which can be connected to
> multiple MACs. For that processor, I anticipate the easiest way to
> resolve this will be to add an additional cell with a "protocol
> controller instance" property.
>
> Each serdes has a unique set of supported protocols (and lanes). The
> support matrix is configured in the device tree. The format of each
> PCCR (protocol configuration register) is modeled. Although the general
> format is typically the same across different SoCs, the specific
> supported protocols (and the values necessary to select them) are
> particular to individual SerDes. A nested structure is used to reduce
> duplication of data.
>
> There are two PLLs, each of which can be used as the master clock for
> each lane. Each PLL has its own reference. For the moment they are
> required, because it simplifies the driver implementation. Absent
> reference clocks can be modeled by a fixed-clock with a rate of 0.
>
> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
> ---
>
> Changes in v3:
> - Manually expand yaml references
> - Add mode configuration to device tree
>
> Changes in v2:
> - Rename to fsl,lynx-10g.yaml
> - Refer to the device in the documentation, rather than the binding
> - Move compatible first
> - Document phy cells in the description
> - Allow a value of 1 for phy-cells. This allows for compatibility with
> the similar (but according to Ioana Ciornei different enough) lynx-28g
> binding.
> - Remove minItems
> - Use list for clock-names
> - Fix example binding having too many cells in regs
> - Add #clock-cells. This will allow using assigned-clocks* to configure
> the PLLs.
> - Document the structure of the compatible strings
>
> .../devicetree/bindings/phy/fsl,lynx-10g.yaml | 311 ++++++++++++++++++
> 1 file changed, 311 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
> new file mode 100644
> index 000000000000..a2c37225bb67
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
> @@ -0,0 +1,311 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/fsl,lynx-10g.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP Lynx 10G SerDes
> +
> +maintainers:
> + - Sean Anderson <sean.anderson@seco.com>
> +
> +description: |
> + These Lynx "SerDes" devices are found in NXP's QorIQ line of processors. The
> + SerDes provides up to eight lanes. Each lane may be configured individually,
> + or may be combined with adjacent lanes for a multi-lane protocol. The SerDes
> + supports a variety of protocols, including up to 10G Ethernet, PCIe, SATA, and
> + others. The specific protocols supported for each lane depend on the
> + particular SoC.
> +
> +definitions:
$defs:
> + fsl,cfg:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 1
> + description: |
> + The configuration value to program into the field.
What field?
> +
> + fsl,first-lane:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 7
> + description: |
> + The first lane in the group configured by fsl,cfg. This lane will have
> + the FIRST_LANE bit set in GCR0. The reset direction will also be set
> + based on whether this property is less than or greater than
> + fsl,last-lane.
> +
> + fsl,last-lane:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 7
> + description: |
> + The last lane configured by fsl,cfg. If this property is absent,
> + then it will default to the value of fsl,first-lane.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - fsl,ls1046a-serdes
> + - fsl,ls1088a-serdes
> + - const: fsl,lynx-10g
> +
> + "#clock-cells":
> + const: 1
> + description: |
> + The cell contains the index of the PLL, starting from 0. Note that when
> + assigning a rate to a PLL, the PLLs' rates are divided by 1000 to avoid
> + overflow. A rate of 5000000 corresponds to 5GHz.
> +
> + "#phy-cells":
> + minimum: 1
> + maximum: 2
> + description: |
> + The cells contain the following arguments:
> + - The first lane in the group. Lanes are numbered based on the register
> + offsets, not the I/O ports. This corresponds to the letter-based ("Lane
> + A") naming scheme, and not the number-based ("Lane 0") naming scheme. On
> + most SoCs, "Lane A" is "Lane 0", but not always.
> + - Last lane. For single-lane protocols, this should be the same as the
> + first lane.
Perhaps a single cell with a lane mask would be simpler.
> + If no lanes in a SerDes can be grouped, then #phy-cells may be 1, and the
> + first cell will specify the only lane in the group.
It is generally easier to have a fixed number of cells.
> +
> + clocks:
> + maxItems: 2
> + description: |
> + Clock for each PLL reference clock input.
> +
> + clock-names:
> + minItems: 2
> + maxItems: 2
> + items:
> + enum:
> + - ref0
> + - ref1
> +
> + reg:
> + maxItems: 1
> +
> +patternProperties:
> + '^pccr-':
> + type: object
> +
> + description: |
> + One of the protocol configuration registers (PCCRs). These contains
> + several fields, each of which mux a particular protocol onto a particular
> + lane.
> +
> + properties:
> + fsl,pccr:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + The index of the PCCR. This is the same as the register name suffix.
> + For example, a node for PCCRB would use a value of '0xb' for an
> + offset of 0x22C (0x200 + 4 * 0xb).
> +
> + patternProperties:
> + '^(q?sgmii|xfi|pcie|sata)-':
> + type: object
> +
> + description: |
> + A configuration field within a PCCR. Each field configures one
> + protocol controller. The value of the field determines the lanes the
> + controller is connected to, if any.
> +
> + properties:
> + fsl,index:
indexes are generally a red flag in binding. What is the index, how does
it correspond to the h/w and why do you need it. If we do end up needing
it, 'reg' is generally how we address some component.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + The index of the field. This corresponds to the suffix in the
What field?
> + documentation. For example, PEXa would be 0, PEXb 1, etc.
> + Generally, higher fields occupy lower bits.
> +
> + If there are any subnodes present, they will be preferred over
> + fsl,cfg et. al.
> +
> + fsl,cfg:
> + $ref: "#/definitions/fsl,cfg"
> +
> + fsl,first-lane:
> + $ref: "#/definitions/fsl,first-lane"
> +
> + fsl,last-lane:
> + $ref: "#/definitions/fsl,last-lane"
Why do you have lane assignments here and in the phy cells?
> +
> + fsl,proto:
> + $ref: /schemas/types.yaml#/definitions/string
> + enum:
> + - sgmii
> + - sgmii25
> + - qsgmii
> + - xfi
> + - pcie
> + - sata
We have standard phy modes already for at least most of these types.
Generally the mode is set in the phy cells.
> + description: |
> + Indicates the basic group protocols supported by this field.
> + Individual protocols are selected by configuring the protocol
> + controller.
> +
> + - sgmii: 1000BASE-X, SGMII, and 1000BASE-KX (depending on the
> + SoC)
> + - sgmii25: 2500BASE-X, 1000BASE-X, SGMII, and 1000BASE-KX
> + (depending on the SoC)
> + - qsgmii: QSGMII
> + - xfi: 10GBASE-R and 10GBASE-KR (depending on the SoC)
> + - pcie: PCIe
> + - sata: SATA
> +
> + patternProperties:
> + '^cfg-':
> + type: object
> +
> + description: |
> + A single field may have multiple values which, when programmed,
> + connect the protocol controller to different lanes. If this is the
> + case, multiple sub-nodes may be provided, each describing a
> + single muxing.
> +
> + properties:
> + fsl,cfg:
> + $ref: "#/definitions/fsl,cfg"
> +
> + fsl,first-lane:
> + $ref: "#/definitions/fsl,first-lane"
> +
> + fsl,last-lane:
> + $ref: "#/definitions/fsl,last-lane"
> +
> + required:
> + - fsl,cfg
> + - fsl,first-lane
> +
> + dependencies:
> + fsl,last-lane:
> + - fsl,first-lane
> +
> + additionalProperties: false
> +
> + required:
> + - fsl,index
> + - fsl,proto
> +
> + dependencies:
> + fsl,last-lane:
> + - fsl,first-lane
> + fsl,cfg:
> + - fsl,first-lane
> + fsl,first-lane:
> + - fsl,cfg
> +
> + # I would like to require either a config subnode or the config
> + # properties (and not both), but from what I can tell that can't be
> + # expressed in json schema. In particular, it is not possible to
> + # require a pattern property.
Indeed, it is not. There's been some proposals.
> +
> + additionalProperties: false
> +
> + required:
> + - fsl,pccr
> +
> + additionalProperties: false
> +
> +required:
> + - "#clock-cells"
> + - "#phy-cells"
> + - compatible
> + - clocks
> + - clock-names
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + serdes1: phy@1ea0000 {
> + #clock-cells = <1>;
> + #phy-cells = <2>;
> + compatible = "fsl,ls1088a-serdes", "fsl,lynx-10g";
> + reg = <0x1ea0000 0x2000>;
> + clocks = <&clk_100mhz>, <&clk_156_mhz>;
> + clock-names = "ref0", "ref1";
> + assigned-clocks = <&serdes1 0>;
> + assigned-clock-rates = <5000000>;
> +
> + pccr-8 {
> + fsl,pccr = <0x8>;
> +
> + sgmii-0 {
> + fsl,index = <0>;
> + fsl,cfg = <0x1>;
> + fsl,first-lane = <3>;
> + fsl,proto = "sgmii";
> + };
> +
> + sgmii-1 {
> + fsl,index = <1>;
> + fsl,cfg = <0x1>;
> + fsl,first-lane = <2>;
> + fsl,proto = "sgmii";
> + };
> +
> + sgmii-2 {
> + fsl,index = <2>;
> + fsl,cfg = <0x1>;
> + fsl,first-lane = <1>;
> + fsl,proto = "sgmii25";
> + };
> +
> + sgmii-3 {
> + fsl,index = <3>;
> + fsl,cfg = <0x1>;
> + fsl,first-lane = <0>;
> + fsl,proto = "sgmii25";
> + };
> + };
> +
> + pccr-9 {
> + fsl,pccr = <0x9>;
> +
> + qsgmii-0 {
> + fsl,index = <0>;
> + fsl,cfg = <0x1>;
> + fsl,first-lane = <3>;
> + fsl,proto = "qsgmii";
> + };
> +
> + qsgmii-1 {
> + fsl,index = <1>;
> + fsl,proto = "qsgmii";
> +
> + cfg-1 {
> + fsl,cfg = <0x1>;
> + fsl,first-lane = <2>;
> + };
> +
> + cfg-2 {
> + fsl,cfg = <0x2>;
> + fsl,first-lane = <0>;
> + };
> + };
> + };
> +
> + pccr-b {
> + fsl,pccr = <0xb>;
> +
> + xfi-0 {
> + fsl,index = <0>;
> + fsl,cfg = <0x1>;
> + fsl,first-lane = <1>;
> + fsl,proto = "xfi";
> + };
> +
> + xfi-1 {
> + fsl,index = <1>;
> + fsl,cfg = <0x1>;
> + fsl,first-lane = <0>;
> + fsl,proto = "xfi";
> + };
> + };
> + };
Other than lane assignments and modes, I don't really understand what
you are trying to do. It all looks too complex and I don't see any other
phy bindings needing something this complex.
Rob
^ permalink raw reply [flat|nested] 30+ messages in thread
* RE: [PATCH net-next v3 42/47] powerpc: dts: qoriq: Add nodes for QSGMII PCSs
2022-07-15 21:59 ` [PATCH net-next v3 42/47] powerpc: dts: qoriq: Add nodes for QSGMII PCSs Sean Anderson
@ 2022-07-21 13:48 ` Camelia Alexandra Groza
2022-07-21 17:51 ` Sean Anderson
0 siblings, 1 reply; 30+ messages in thread
From: Camelia Alexandra Groza @ 2022-07-21 13:48 UTC (permalink / raw)
To: Sean Anderson, David S . Miller, Jakub Kicinski, Madalin Bucur,
netdev@vger.kernel.org
Cc: devicetree@vger.kernel.org, Leo Li, Sean Anderson,
linuxppc-dev@lists.ozlabs.org, Russell King,
linux-kernel@vger.kernel.org, Eric Dumazet, Rob Herring,
Paul Mackerras, Krzysztof Kozlowski, Paolo Abeni, Shawn Guo,
linux-arm-kernel@lists.infradead.org
> -----Original Message-----
> From: Linuxppc-dev <linuxppc-dev-
> bounces+camelia.groza=nxp.com@lists.ozlabs.org> On Behalf Of Sean
> Anderson
> Sent: Saturday, July 16, 2022 1:00
> To: David S . Miller <davem@davemloft.net>; Jakub Kicinski
> <kuba@kernel.org>; Madalin Bucur <madalin.bucur@nxp.com>;
> netdev@vger.kernel.org
> Cc: devicetree@vger.kernel.org; Leo Li <leoyang.li@nxp.com>; Sean
> Anderson <sean.anderson@seco.com>; linuxppc-dev@lists.ozlabs.org;
> Russell King <linux@armlinux.org.uk>; linux-kernel@vger.kernel.org; Eric
> Dumazet <edumazet@google.com>; Rob Herring <robh+dt@kernel.org>;
> Paul Mackerras <paulus@samba.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@linaro.org>; Paolo Abeni <pabeni@redhat.com>;
> Shawn Guo <shawnguo@kernel.org>; linux-arm-kernel@lists.infradead.org
> Subject: [PATCH net-next v3 42/47] powerpc: dts: qoriq: Add nodes for
> QSGMII PCSs
>
> Now that we actually read registers from QSGMII PCSs, it's important
> that we have the correct address (instead of hoping that we're the MAC
> with all the QSGMII PCSs on its bus). This adds nodes for the QSGMII
> PCSs. They have the same addresses on all SoCs (e.g. if QSGMIIA is
> present it's used for MACs 1 through 4).
>
> Since the first QSGMII PCSs share an address with the SGMII and XFI
> PCSs, we only add new nodes for PCSs 2-4. This avoids address conflicts
> on the bus.
>
> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
MAC1 and MAC2 can be XFI on T2080. This needs to be reflected in qoriq-fman3-0-1g-0.dtsi
and qoriq-fman3-0-1g-1.dtsi
The two associated netdevs fail to probe on a T2080RDB without "xfi" added to the pcs-names:
fsl_dpaa_mac ffe4e0000.ethernet (unnamed net_device) (uninitialized): failed to validate link configuration for in-band status
fsl_dpaa_mac ffe4e0000.ethernet: error -EINVAL: Could not create phylink
fsl_dpa: probe of dpaa-ethernet.0 failed with error -22
> ---
>
> Changes in v3:
> - Add compatibles for QSGMII PCSs
> - Split arm and powerpcs dts updates
>
> Changes in v2:
> - New
>
> .../boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi | 3 ++-
> arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi | 10 +++++++++-
> .../boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi | 10 +++++++++-
> arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi | 10 +++++++++-
> arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi | 3 ++-
> arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi | 10 +++++++++-
> arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi | 10 +++++++++-
> arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi | 10 +++++++++-
> arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi | 3 ++-
> arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi | 10 +++++++++-
> arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi | 10 +++++++++-
> arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi | 10 +++++++++-
> arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi | 3 ++-
> arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi | 10 +++++++++-
> arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi | 10 +++++++++-
> arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi | 10 +++++++++-
> arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi | 3 ++-
> arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi | 10 +++++++++-
> 18 files changed, 127 insertions(+), 18 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
> index baa0c503e741..db169d630db3 100644
> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
> @@ -55,7 +55,8 @@ ethernet@e0000 {
> reg = <0xe0000 0x1000>;
> fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
> ptp-timer = <&ptp_timer0>;
> - pcsphy-handle = <&pcsphy0>;
> + pcsphy-handle = <&pcsphy0>, <&pcsphy0>;
> + pcs-names = "sgmii", "qsgmii";
> };
>
> mdio@e1000 {
> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
> index 93095600e808..e80ad8675be8 100644
> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
> @@ -52,7 +52,15 @@ ethernet@f0000 {
> compatible = "fsl,fman-memac";
> reg = <0xf0000 0x1000>;
> fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
> - pcsphy-handle = <&pcsphy6>;
> + pcsphy-handle = <&pcsphy6>, <&qsgmiib_pcs2>,
> <&pcsphy6>;
> + pcs-names = "sgmii", "qsgmii", "xfi";
> + };
> +
> + mdio@e9000 {
> + qsgmiib_pcs2: ethernet-pcs@2 {
> + compatible = "fsl,lynx-pcs";
> + reg = <2>;
> + };
> };
>
> mdio@f1000 {
> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
> index ff4bd38f0645..6a6f51842ad5 100644
> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
> @@ -55,7 +55,15 @@ ethernet@e2000 {
> reg = <0xe2000 0x1000>;
> fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
> ptp-timer = <&ptp_timer0>;
> - pcsphy-handle = <&pcsphy1>;
> + pcsphy-handle = <&pcsphy1>, <&qsgmiia_pcs1>;
> + pcs-names = "sgmii", "qsgmii";
> + };
> +
> + mdio@e1000 {
> + qsgmiia_pcs1: ethernet-pcs@1 {
> + compatible = "fsl,lynx-pcs";
> + reg = <1>;
> + };
> };
>
> mdio@e3000 {
> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
> index 1fa38ed6f59e..543da5493e40 100644
> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
> @@ -52,7 +52,15 @@ ethernet@f2000 {
> compatible = "fsl,fman-memac";
> reg = <0xf2000 0x1000>;
> fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
> - pcsphy-handle = <&pcsphy7>;
> + pcsphy-handle = <&pcsphy7>, <&qsgmiib_pcs3>,
> <&pcsphy7>;
> + pcs-names = "sgmii", "qsgmii", "xfi";
> + };
> +
> + mdio@e9000 {
> + qsgmiib_pcs3: ethernet-pcs@3 {
> + compatible = "fsl,lynx-pcs";
> + reg = <3>;
> + };
> };
>
> mdio@f3000 {
> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi
> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi
> index a8cc9780c0c4..ce76725e6eb2 100644
> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi
> @@ -51,7 +51,8 @@ ethernet@e0000 {
> reg = <0xe0000 0x1000>;
> fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
> ptp-timer = <&ptp_timer0>;
> - pcsphy-handle = <&pcsphy0>;
> + pcsphy-handle = <&pcsphy0>, <&pcsphy0>;
> + pcs-names = "sgmii", "qsgmii";
> };
>
> mdio@e1000 {
> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi
> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi
> index 8b8bd70c9382..f3af67df4767 100644
> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi
> @@ -51,7 +51,15 @@ ethernet@e2000 {
> reg = <0xe2000 0x1000>;
> fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
> ptp-timer = <&ptp_timer0>;
> - pcsphy-handle = <&pcsphy1>;
> + pcsphy-handle = <&pcsphy1>, <&qsgmiia_pcs1>;
> + pcs-names = "sgmii", "qsgmii";
> + };
> +
> + mdio@e1000 {
> + qsgmiia_pcs1: ethernet-pcs@1 {
> + compatible = "fsl,lynx-pcs";
> + reg = <1>;
> + };
> };
>
> mdio@e3000 {
> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi
> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi
> index 619c880b54d8..f6d74de84bfe 100644
> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi
> @@ -51,7 +51,15 @@ ethernet@e4000 {
> reg = <0xe4000 0x1000>;
> fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
> ptp-timer = <&ptp_timer0>;
> - pcsphy-handle = <&pcsphy2>;
> + pcsphy-handle = <&pcsphy2>, <&qsgmiia_pcs2>;
> + pcs-names = "sgmii", "qsgmii";
> + };
> +
> + mdio@e1000 {
> + qsgmiia_pcs2: ethernet-pcs@2 {
> + compatible = "fsl,lynx-pcs";
> + reg = <2>;
> + };
> };
>
> mdio@e5000 {
> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi
> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi
> index d7ebb73a400d..6e091d8ae9e2 100644
> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi
> @@ -51,7 +51,15 @@ ethernet@e6000 {
> reg = <0xe6000 0x1000>;
> fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
> ptp-timer = <&ptp_timer0>;
> - pcsphy-handle = <&pcsphy3>;
> + pcsphy-handle = <&pcsphy3>, <&qsgmiia_pcs3>;
> + pcs-names = "sgmii", "qsgmii";
> + };
> +
> + mdio@e1000 {
> + qsgmiia_pcs3: ethernet-pcs@3 {
> + compatible = "fsl,lynx-pcs";
> + reg = <3>;
> + };
> };
>
> mdio@e7000 {
> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi
> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi
> index b151d696a069..e2174c0fc841 100644
> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi
> @@ -51,7 +51,8 @@ ethernet@e8000 {
> reg = <0xe8000 0x1000>;
> fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
> ptp-timer = <&ptp_timer0>;
> - pcsphy-handle = <&pcsphy4>;
> + pcsphy-handle = <&pcsphy4>, <&pcsphy4>;
> + pcs-names = "sgmii", "qsgmii";
> };
>
> mdio@e9000 {
> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi
> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi
> index adc0ae0013a3..9106815bd63e 100644
> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi
> @@ -51,7 +51,15 @@ ethernet@ea000 {
> reg = <0xea000 0x1000>;
> fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
> ptp-timer = <&ptp_timer0>;
> - pcsphy-handle = <&pcsphy5>;
> + pcsphy-handle = <&pcsphy5>, <&qsgmiib_pcs1>;
> + pcs-names = "sgmii", "qsgmii";
> + };
> +
> + mdio@e9000 {
> + qsgmiib_pcs1: ethernet-pcs@1 {
> + compatible = "fsl,lynx-pcs";
> + reg = <1>;
> + };
> };
>
> mdio@eb000 {
> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi
> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi
> index 435047e0e250..a3c1538dfda1 100644
> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi
> @@ -52,7 +52,15 @@ ethernet@f0000 {
> compatible = "fsl,fman-memac";
> reg = <0xf0000 0x1000>;
> fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
> - pcsphy-handle = <&pcsphy14>;
> + pcsphy-handle = <&pcsphy14>, <&qsgmiid_pcs2>,
> <&pcsphy14>;
> + pcs-names = "sgmii", "qsgmii", "xfi";
> + };
> +
> + mdio@e9000 {
> + qsgmiid_pcs2: ethernet-pcs@2 {
> + compatible = "fsl,lynx-pcs";
> + reg = <2>;
> + };
> };
>
> mdio@f1000 {
> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi
> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi
> index c098657cca0a..c024517e70d6 100644
> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi
> @@ -52,7 +52,15 @@ ethernet@f2000 {
> compatible = "fsl,fman-memac";
> reg = <0xf2000 0x1000>;
> fsl,fman-ports = <&fman1_rx_0x11 &fman1_tx_0x31>;
> - pcsphy-handle = <&pcsphy15>;
> + pcsphy-handle = <&pcsphy15>, <&qsgmiid_pcs3>,
> <&pcsphy15>;
> + pcs-names = "sgmii", "qsgmii", "xfi";
> + };
> +
> + mdio@e9000 {
> + qsgmiid_pcs3: ethernet-pcs@3 {
> + compatible = "fsl,lynx-pcs";
> + reg = <3>;
> + };
> };
>
> mdio@f3000 {
> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi
> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi
> index 9d06824815f3..16fb299f615a 100644
> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi
> @@ -51,7 +51,8 @@ ethernet@e0000 {
> reg = <0xe0000 0x1000>;
> fsl,fman-ports = <&fman1_rx_0x08 &fman1_tx_0x28>;
> ptp-timer = <&ptp_timer1>;
> - pcsphy-handle = <&pcsphy8>;
> + pcsphy-handle = <&pcsphy8>, <&pcsphy8>;
> + pcs-names = "sgmii", "qsgmii";
> };
>
> mdio@e1000 {
> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi
> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi
> index 70e947730c4b..75cecbef8469 100644
> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi
> @@ -51,7 +51,15 @@ ethernet@e2000 {
> reg = <0xe2000 0x1000>;
> fsl,fman-ports = <&fman1_rx_0x09 &fman1_tx_0x29>;
> ptp-timer = <&ptp_timer1>;
> - pcsphy-handle = <&pcsphy9>;
> + pcsphy-handle = <&pcsphy9>, <&qsgmiic_pcs1>;
> + pcs-names = "sgmii", "qsgmii";
> + };
> +
> + mdio@e1000 {
> + qsgmiic_pcs1: ethernet-pcs@1 {
> + compatible = "fsl,lynx-pcs";
> + reg = <1>;
> + };
> };
>
> mdio@e3000 {
> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi
> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi
> index ad96e6529595..98c1d27f17e7 100644
> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi
> @@ -51,7 +51,15 @@ ethernet@e4000 {
> reg = <0xe4000 0x1000>;
> fsl,fman-ports = <&fman1_rx_0x0a &fman1_tx_0x2a>;
> ptp-timer = <&ptp_timer1>;
> - pcsphy-handle = <&pcsphy10>;
> + pcsphy-handle = <&pcsphy10>, <&qsgmiic_pcs2>;
> + pcs-names = "sgmii", "qsgmii";
> + };
> +
> + mdio@e1000 {
> + qsgmiic_pcs2: ethernet-pcs@2 {
> + compatible = "fsl,lynx-pcs";
> + reg = <2>;
> + };
> };
>
> mdio@e5000 {
> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi
> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi
> index 034bc4b71f7a..203a00036f17 100644
> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi
> @@ -51,7 +51,15 @@ ethernet@e6000 {
> reg = <0xe6000 0x1000>;
> fsl,fman-ports = <&fman1_rx_0x0b &fman1_tx_0x2b>;
> ptp-timer = <&ptp_timer1>;
> - pcsphy-handle = <&pcsphy11>;
> + pcsphy-handle = <&pcsphy11>, <&qsgmiic_pcs3>;
> + pcs-names = "sgmii", "qsgmii";
> + };
> +
> + mdio@e1000 {
> + qsgmiic_pcs3: ethernet-pcs@3 {
> + compatible = "fsl,lynx-pcs";
> + reg = <3>;
> + };
> };
>
> mdio@e7000 {
> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi
> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi
> index 93ca23d82b39..9366935ebc02 100644
> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi
> @@ -51,7 +51,8 @@ ethernet@e8000 {
> reg = <0xe8000 0x1000>;
> fsl,fman-ports = <&fman1_rx_0x0c &fman1_tx_0x2c>;
> ptp-timer = <&ptp_timer1>;
> - pcsphy-handle = <&pcsphy12>;
> + pcsphy-handle = <&pcsphy12>, <&pcsphy12>;
> + pcs-names = "sgmii", "qsgmii";
> };
>
> mdio@e9000 {
> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi
> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi
> index 23b3117a2fd2..39f7c6133017 100644
> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi
> @@ -51,7 +51,15 @@ ethernet@ea000 {
> reg = <0xea000 0x1000>;
> fsl,fman-ports = <&fman1_rx_0x0d &fman1_tx_0x2d>;
> ptp-timer = <&ptp_timer1>;
> - pcsphy-handle = <&pcsphy13>;
> + pcsphy-handle = <&pcsphy13>, <&qsgmiid_pcs1>;
> + pcs-names = "sgmii", "qsgmii";
> + };
> +
> + mdio@e9000 {
> + qsgmiid_pcs1: ethernet-pcs@1 {
> + compatible = "fsl,lynx-pcs";
> + reg = <1>;
> + };
> };
>
> mdio@eb000 {
> --
> 2.35.1.1320.gc452695387.dirty
^ permalink raw reply [flat|nested] 30+ messages in thread
* RE: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes bindings
2022-07-15 21:59 ` [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: " Sean Anderson
@ 2022-07-21 14:20 ` Camelia Alexandra Groza
2022-07-21 15:40 ` Sean Anderson
0 siblings, 1 reply; 30+ messages in thread
From: Camelia Alexandra Groza @ 2022-07-21 14:20 UTC (permalink / raw)
To: Sean Anderson, David S . Miller, Jakub Kicinski, Madalin Bucur,
netdev@vger.kernel.org
Cc: Paolo Abeni, Eric Dumazet, linux-arm-kernel@lists.infradead.org,
Russell King, linux-kernel@vger.kernel.org, Sean Anderson,
Kishon Vijay Abraham I, Krzysztof Kozlowski, Leo Li, Rob Herring,
Shawn Guo, Vinod Koul, devicetree@vger.kernel.org,
linux-phy@lists.infradead.org
> -----Original Message-----
> From: Sean Anderson <sean.anderson@seco.com>
> Sent: Saturday, July 16, 2022 1:00
> To: David S . Miller <davem@davemloft.net>; Jakub Kicinski
> <kuba@kernel.org>; Madalin Bucur <madalin.bucur@nxp.com>;
> netdev@vger.kernel.org
> Cc: Paolo Abeni <pabeni@redhat.com>; Eric Dumazet
> <edumazet@google.com>; linux-arm-kernel@lists.infradead.org; Russell
> King <linux@armlinux.org.uk>; linux-kernel@vger.kernel.org; Sean Anderson
> <sean.anderson@seco.com>; Kishon Vijay Abraham I <kishon@ti.com>;
> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Leo Li
> <leoyang.li@nxp.com>; Rob Herring <robh+dt@kernel.org>; Shawn Guo
> <shawnguo@kernel.org>; Vinod Koul <vkoul@kernel.org>;
> devicetree@vger.kernel.org; linux-phy@lists.infradead.org
> Subject: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes
> bindings
>
> This adds appropriate bindings for the macs which use the SerDes. The
> 156.25MHz fixed clock is a crystal. The 100MHz clocks (there are
> actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is
> no driver for this device (and as far as I know all you can do with the
> 100MHz clocks is gate them), so I have chosen to model it as a single
> fixed clock.
>
> Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
> This means that Lane A (what the driver thinks is lane 0) uses pins
> SD1_TX3_P/N.
>
> Because this will break ethernet if the serdes is not enabled, enable
> the serdes driver by default on Layerscape.
>
> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
> ---
> Please let me know if there is a better/more specific config I can use
> here.
>
> (no changes since v1)
My LS1046ARDB hangs at boot with this patch right after the second SerDes is probed,
right before the point where the PCI host bridge is registered. I can get around this
either by disabling the second SerDes node from the device tree, or disabling
CONFIG_PCI_LAYERSCAPE at build.
I haven't debugged it more but there seems to be an issue here.
> .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 34 +++++++++++++++++++
> drivers/phy/freescale/Kconfig | 1 +
> 2 files changed, 35 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
> b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
> index 7025aad8ae89..4f4dd0ed8c53 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
> @@ -26,6 +26,32 @@ aliases {
> chosen {
> stdout-path = "serial0:115200n8";
> };
> +
> + clocks {
> + clk_100mhz: clock-100mhz {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + };
> +
> + clk_156mhz: clock-156mhz {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <156250000>;
> + };
> + };
> +};
> +
> +&serdes1 {
> + clocks = <&clk_100mhz>, <&clk_156mhz>;
> + clock-names = "ref0", "ref1";
> + status = "okay";
> +};
> +
> +&serdes2 {
> + clocks = <&clk_100mhz>, <&clk_100mhz>;
> + clock-names = "ref0", "ref1";
> + status = "okay";
> };
>
> &duart0 {
> @@ -140,21 +166,29 @@ ethernet@e6000 {
> ethernet@e8000 {
> phy-handle = <&sgmii_phy1>;
> phy-connection-type = "sgmii";
> + phys = <&serdes1 1>;
> + phy-names = "serdes";
> };
>
> ethernet@ea000 {
> phy-handle = <&sgmii_phy2>;
> phy-connection-type = "sgmii";
> + phys = <&serdes1 0>;
> + phy-names = "serdes";
> };
>
> ethernet@f0000 { /* 10GEC1 */
> phy-handle = <&aqr106_phy>;
> phy-connection-type = "xgmii";
> + phys = <&serdes1 3>;
> + phy-names = "serdes";
> };
>
> ethernet@f2000 { /* 10GEC2 */
> fixed-link = <0 1 1000 0 0>;
> phy-connection-type = "xgmii";
> + phys = <&serdes1 2>;
> + phy-names = "serdes";
> };
>
> mdio@fc000 {
> diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
> index fe2a3efe0ba4..9595666213d0 100644
> --- a/drivers/phy/freescale/Kconfig
> +++ b/drivers/phy/freescale/Kconfig
> @@ -43,6 +43,7 @@ config PHY_FSL_LYNX_10G
> tristate "Freescale Layerscale Lynx 10G SerDes support"
> select GENERIC_PHY
> select REGMAP_MMIO
> + default y if ARCH_LAYERSCAPE
> help
> This adds support for the Lynx "SerDes" devices found on various
> QorIQ
> SoCs. There may be up to four SerDes devices on each SoC, and
> each
> --
> 2.35.1.1320.gc452695387.dirty
^ permalink raw reply [flat|nested] 30+ messages in thread
* RE: [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink
2022-07-15 21:59 [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink Sean Anderson
` (9 preceding siblings ...)
2022-07-15 21:59 ` [PATCH net-next v3 47/47] [WIP] arm64: dts: ls1088ardb: " Sean Anderson
@ 2022-07-21 14:26 ` Camelia Alexandra Groza
2022-07-21 15:39 ` Sean Anderson
10 siblings, 1 reply; 30+ messages in thread
From: Camelia Alexandra Groza @ 2022-07-21 14:26 UTC (permalink / raw)
To: Sean Anderson, David S . Miller, Jakub Kicinski, Madalin Bucur,
netdev@vger.kernel.org
Cc: Paolo Abeni, Eric Dumazet, linux-arm-kernel@lists.infradead.org,
Russell King, linux-kernel@vger.kernel.org, Sean Anderson,
Alexandru Marginean, Andrew Lunn, Benjamin Herrenschmidt,
Heiner Kallweit, Ioana Ciornei, Jonathan Corbet,
Kishon Vijay Abraham I, Krzysztof Kozlowski, Leo Li,
Michael Ellerman, Paul Mackerras, Rob Herring, Shawn Guo,
Vinod Koul, Vladimir Oltean, devicetree@vger.kernel.org,
linux-doc@vger.kernel.org, linux-phy@lists.infradead.org,
linuxppc-dev@lists.ozlabs.org
> -----Original Message-----
> From: Sean Anderson <sean.anderson@seco.com>
> Sent: Saturday, July 16, 2022 0:59
> To: David S . Miller <davem@davemloft.net>; Jakub Kicinski
> <kuba@kernel.org>; Madalin Bucur <madalin.bucur@nxp.com>;
> netdev@vger.kernel.org
> Cc: Paolo Abeni <pabeni@redhat.com>; Eric Dumazet
> <edumazet@google.com>; linux-arm-kernel@lists.infradead.org; Russell
> King <linux@armlinux.org.uk>; linux-kernel@vger.kernel.org; Sean Anderson
> <sean.anderson@seco.com>; Alexandru Marginean
> <alexandru.marginean@nxp.com>; Andrew Lunn <andrew@lunn.ch>;
> Benjamin Herrenschmidt <benh@kernel.crashing.org>; Heiner Kallweit
> <hkallweit1@gmail.com>; Ioana Ciornei <ioana.ciornei@nxp.com>; Jonathan
> Corbet <corbet@lwn.net>; Kishon Vijay Abraham I <kishon@ti.com>;
> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Leo Li
> <leoyang.li@nxp.com>; Michael Ellerman <mpe@ellerman.id.au>; Paul
> Mackerras <paulus@samba.org>; Rob Herring <robh+dt@kernel.org>;
> Shawn Guo <shawnguo@kernel.org>; Vinod Koul <vkoul@kernel.org>;
> Vladimir Oltean <olteanv@gmail.com>; devicetree@vger.kernel.org; linux-
> doc@vger.kernel.org; linux-phy@lists.infradead.org; linuxppc-
> dev@lists.ozlabs.org
> Subject: [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink
>
> This series converts the DPAA driver to phylink. Additionally,
> it also adds a serdes driver to allow for dynamic reconfiguration
> between 1g and 10g interfaces (such as in an SFP+ slot). These changes
> are submitted together for this RFT, but they will eventually be
> submitted separately to the appropriate subsystem maintainers.
>
> I have tried to maintain backwards compatibility with existing device
> trees whereever possible. However, one area where I was unable to
> achieve this was with QSGMII. Please refer to patch 4 for details.
>
> All mac drivers have now been converted. I would greatly appreciate if
> anyone has QorIQ boards they can test/debug this series on. I only have an
> LS1046ARDB. Everything but QSGMII should work without breakage; QSGMII
> needs patches 42 and 43.
>
> The serdes driver is mostly functional (except for XFI). This series
> only adds support for the LS1046ARDB SerDes (and untested LS1088ARDB),
> but it should be fairly straightforward to add support for other SoCs
> and boards (see Documentation/driver-api/phy/qoriq.rst).
>
> This is the last spin of this series with all patches included. After next
> week (depending on feedback) I will resend the patches broken up as
> follows:
> - 5: 1000BASE-KX support
> - 1, 6, 44, 45: Lynx 10G support
> - 7-10, 12-14: Phy rate adaptation support
> - 2-4, 15-43, 46, 47: DPAA phylink conversion
Please also send patches 15-38 separately from the DPAA1 SerDes and phylink set for easier review
> Patches 15-19 were first submitted as [1].
>
> [1] https://lore.kernel.org/netdev/20220531195851.1592220-1-sean.anderson@seco.com/
>
> Changes in v3:
> - Manually expand yaml references
> - Add mode configuration to device tree
> - Expand pcs-handle to an array
> - Incorperate some minor changes into the first FMan binding commit
> - Add vendor prefix 'fsl,' to rgmii and mii properties.
> - Set maxItems for pcs-names
> - Remove phy-* properties from example because dt-schema complains and
> I
> can't be bothered to figure out how to make it work.
> - Add pcs-handle as a preferred version of pcsphy-handle
> - Deprecate pcsphy-handle
> - Remove mii/rmii properties
> - Add 1000BASE-KX interface mode
> - Rename remaining references to QorIQ SerDes to Lynx 10G
> - Fix PLL enable sequence by waiting for our reset request to be cleared
> before continuing. Do the same for the lock, even though it isn't as
> critical. Because we will delay for 1.5ms on average, use prepare
> instead of enable so we can sleep.
> - Document the status of each protocol
> - Fix offset of several bitfields in RECR0
> - Take into account PLLRST_B, SDRST_B, and SDEN when considering whether
> a PLL is "enabled."
> - Only power off unused lanes.
> - Split mode lane mask into first/last lane (like group)
> - Read modes from device tree
> - Use caps to determine whether KX/KR are supported
> - Move modes to lynx_priv
> - Ensure that the protocol controller is not already in-use when we try
> to configure a new mode. This should only occur if the device tree is
> misconfigured (e.g. when QSGMII is selected on two lanes but there is
> only one QSGMII controller).
> - Split PLL drivers off into their own file
> - Add clock for "ext_dly" instead of writing the bit directly (and
> racing with any clock code).
> - Use kasprintf instead of open-coding the snprintf dance
> - Support 1000BASE-KX in lynx_lookup_proto. This still requires PCS
> support, so nothing is truly "enabled" yet.
> - Add support for phy rate adaptation
> - Support differing link speeds and interface speeds
> - Adjust advertisement based on rate adaptation
> - Adjust link settings based on rate adaptation
> - Add support for CRS-based rate adaptation
> - Add support for AQR115
> - Add some additional phy interfaces
> - Add support for aquantia rate adaptation
> - Put the PCS mdiodev only after we are done with it (since the PCS
> does not perform a get itself).
> - Remove _return label from memac_initialization in favor of returning
> directly
> - Fix grabbing the default PCS not checking for -ENODATA from
> of_property_match_string
> - Set DTSEC_ECNTRL_R100M in dtsec_link_up instead of dtsec_mac_config
> - Remove rmii/mii properties
> - Replace 1000Base... with 1000BASE... to match IEEE capitalization
> - Add compatibles for QSGMII PCSs
> - Split arm and powerpcs dts updates
> - Describe modes in device tree
> - ls1088a: Add serdes bindings
>
> Changes in v2:
> - Rename to fsl,lynx-10g.yaml
> - Refer to the device in the documentation, rather than the binding
> - Move compatible first
> - Document phy cells in the description
> - Allow a value of 1 for phy-cells. This allows for compatibility with
> the similar (but according to Ioana Ciornei different enough) lynx-28g
> binding.
> - Remove minItems
> - Use list for clock-names
> - Fix example binding having too many cells in regs
> - Add #clock-cells. This will allow using assigned-clocks* to configure
> the PLLs.
> - Document the structure of the compatible strings
> - Convert FMan MAC bindings to yaml
> - Better document how we select which PCS to use in the default case
> - Rename driver to Lynx 10G (etc.)
> - Fix not clearing group->pll after disabling it
> - Support 1 and 2 phy-cells
> - Power off lanes during probe
> - Clear SGMIIaCR1_PCS_EN during probe
> - Rename LYNX_PROTO_UNKNOWN to LYNX_PROTO_NONE
> - Handle 1000BASE-KX in lynx_proto_mode_prep
> - Remove some unused variables
> - Fix prototype for dtsec_initialization
> - Fix warning if sizeof(void *) != sizeof(resource_size_t)
> - Specify type of mac_dev for exception_cb
> - Add helper for sanity checking cgr ops
> - Add CGR update function
> - Adjust queue depth on rate change
> - Move PCS_LYNX dependency to fman Kconfig
> - Remove unused variable slow_10g_if
> - Restrict valid link modes based on the phy interface. This is easier
> to set up, and mostly captures what I intended to do the first time.
> We now have a custom validate which restricts half-duplex for some SoCs
> for RGMII, but generally just uses the default phylink validate.
> - Configure the SerDes in enable/disable
> - Properly implement all ethtool ops and ioctls. These were mostly
> stubbed out just enough to compile last time.
> - Convert 10GEC and dTSEC as well
> - Fix capitalization of mEMAC in commit messages
> - Add nodes for QSGMII PCSs
> - Add nodes for QSGMII PCSs
> - Use one phy cell for SerDes1, since no lanes can be grouped
> - Disable SerDes by default to prevent breaking boards inadvertently.
>
> Sean Anderson (47):
> dt-bindings: phy: Add Lynx 10G phy binding
> dt-bindings: net: Expand pcs-handle to an array
> dt-bindings: net: Convert FMan MAC bindings to yaml
> dt-bindings: net: fman: Add additional interface properties
> net: phy: Add 1000BASE-KX interface mode
> [RFT] phy: fsl: Add Lynx 10G SerDes driver
> net: phy: Add support for rate adaptation
> net: phylink: Support differing link speeds and interface speeds
> net: phylink: Adjust advertisement based on rate adaptation
> net: phylink: Adjust link settings based on rate adaptation
> [RFC] net: phylink: Add support for CRS-based rate adaptation
> net: phy: aquantia: Add support for AQR115
> net: phy: aquantia: Add some additional phy interfaces
> net: phy: aquantia: Add support for rate adaptation
> net: fman: Convert to SPDX identifiers
> net: fman: Don't pass comm_mode to enable/disable
> net: fman: Store en/disable in mac_device instead of mac_priv_s
> net: fman: dtsec: Always gracefully stop/start
> net: fman: Get PCS node in per-mac init
> net: fman: Store initialization function in match data
> net: fman: Move struct dev to mac_device
> net: fman: Configure fixed link in memac_initialization
> net: fman: Export/rename some common functions
> net: fman: memac: Use params instead of priv for max_speed
> net: fman: Move initialization to mac-specific files
> net: fman: Mark mac methods static
> net: fman: Inline several functions into initialization
> net: fman: Remove internal_phy_node from params
> net: fman: Map the base address once
> net: fman: Pass params directly to mac init
> net: fman: Use mac_dev for some params
> net: fman: Specify type of mac_dev for exception_cb
> net: fman: Clean up error handling
> net: fman: Change return type of disable to void
> net: dpaa: Use mac_dev variable in dpaa_netdev_init
> soc: fsl: qbman: Add helper for sanity checking cgr ops
> soc: fsl: qbman: Add CGR update function
> net: dpaa: Adjust queue depth on rate change
> net: fman: memac: Add serdes support
> net: fman: memac: Use lynx pcs driver
> [RFT] net: dpaa: Convert to phylink
> powerpc: dts: qoriq: Add nodes for QSGMII PCSs
> arm64: dts: layerscape: Add nodes for QSGMII PCSs
> arm64: dts: ls1046a: Add serdes bindings
> arm64: dts: ls1088a: Add serdes bindings
> arm64: dts: ls1046ardb: Add serdes bindings
> [WIP] arm64: dts: ls1088ardb: Add serdes bindings
>
> .../bindings/net/dsa/renesas,rzn1-a5psw.yaml | 1 +
> .../bindings/net/ethernet-controller.yaml | 10 +-
> .../bindings/net/fsl,fman-dtsec.yaml | 172 +++
> .../bindings/net/fsl,qoriq-mc-dpmac.yaml | 2 +-
> .../devicetree/bindings/net/fsl-fman.txt | 133 +-
> .../devicetree/bindings/phy/fsl,lynx-10g.yaml | 311 ++++
> Documentation/driver-api/phy/index.rst | 1 +
> Documentation/driver-api/phy/lynx_10g.rst | 73 +
> MAINTAINERS | 6 +
> .../boot/dts/freescale/fsl-ls1043-post.dtsi | 24 +
> .../boot/dts/freescale/fsl-ls1046-post.dtsi | 25 +
> .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 34 +
> .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 179 +++
> .../boot/dts/freescale/fsl-ls1088a-rdb.dts | 87 ++
> .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 96 ++
> .../fsl/qoriq-fman3-0-10g-0-best-effort.dtsi | 3 +-
> .../boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi | 10 +-
> .../fsl/qoriq-fman3-0-10g-1-best-effort.dtsi | 10 +-
> .../boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi | 10 +-
> .../boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi | 3 +-
> .../boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi | 10 +-
> .../boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi | 10 +-
> .../boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi | 10 +-
> .../boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi | 3 +-
> .../boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi | 10 +-
> .../boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi | 10 +-
> .../boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi | 10 +-
> .../boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi | 3 +-
> .../boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi | 10 +-
> .../boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi | 10 +-
> .../boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi | 10 +-
> .../boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi | 3 +-
> .../boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi | 10 +-
> drivers/net/ethernet/freescale/dpaa/Kconfig | 4 +-
> .../net/ethernet/freescale/dpaa/dpaa_eth.c | 132 +-
> .../ethernet/freescale/dpaa/dpaa_eth_sysfs.c | 2 +-
> .../ethernet/freescale/dpaa/dpaa_ethtool.c | 90 +-
> drivers/net/ethernet/freescale/fman/Kconfig | 4 +-
> drivers/net/ethernet/freescale/fman/fman.c | 31 +-
> drivers/net/ethernet/freescale/fman/fman.h | 31 +-
> .../net/ethernet/freescale/fman/fman_dtsec.c | 674 ++++-----
> .../net/ethernet/freescale/fman/fman_dtsec.h | 58 +-
> .../net/ethernet/freescale/fman/fman_keygen.c | 29 +-
> .../net/ethernet/freescale/fman/fman_keygen.h | 29 +-
> .../net/ethernet/freescale/fman/fman_mac.h | 34 +-
> .../net/ethernet/freescale/fman/fman_memac.c | 864 +++++------
> .../net/ethernet/freescale/fman/fman_memac.h | 57 +-
> .../net/ethernet/freescale/fman/fman_muram.c | 31 +-
> .../net/ethernet/freescale/fman/fman_muram.h | 32 +-
> .../net/ethernet/freescale/fman/fman_port.c | 29 +-
> .../net/ethernet/freescale/fman/fman_port.h | 29 +-
> drivers/net/ethernet/freescale/fman/fman_sp.c | 29 +-
> drivers/net/ethernet/freescale/fman/fman_sp.h | 28 +-
> .../net/ethernet/freescale/fman/fman_tgec.c | 274 ++--
> .../net/ethernet/freescale/fman/fman_tgec.h | 54 +-
> drivers/net/ethernet/freescale/fman/mac.c | 653 +--------
> drivers/net/ethernet/freescale/fman/mac.h | 66 +-
> drivers/net/phy/aquantia_main.c | 86 +-
> drivers/net/phy/phy.c | 21 +
> drivers/net/phy/phylink.c | 161 +-
> drivers/phy/freescale/Kconfig | 20 +
> drivers/phy/freescale/Makefile | 3 +
> drivers/phy/freescale/lynx-10g.h | 36 +
> drivers/phy/freescale/phy-fsl-lynx-10g-clk.c | 438 ++++++
> drivers/phy/freescale/phy-fsl-lynx-10g.c | 1297 +++++++++++++++++
> drivers/soc/fsl/qbman/qman.c | 76 +-
> include/linux/phy.h | 42 +
> include/linux/phylink.h | 12 +-
> include/soc/fsl/qman.h | 9 +
> 69 files changed, 4408 insertions(+), 2356 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/net/fsl,fman-
> dtsec.yaml
> create mode 100644 Documentation/devicetree/bindings/phy/fsl,lynx-
> 10g.yaml
> create mode 100644 Documentation/driver-api/phy/lynx_10g.rst
> create mode 100644 drivers/phy/freescale/lynx-10g.h
> create mode 100644 drivers/phy/freescale/phy-fsl-lynx-10g-clk.c
> create mode 100644 drivers/phy/freescale/phy-fsl-lynx-10g.c
>
> --
> 2.35.1.1320.gc452695387.dirty
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH net-next v3 03/47] dt-bindings: net: Convert FMan MAC bindings to yaml
2022-07-16 22:47 ` Sean Anderson
@ 2022-07-21 14:42 ` Krzysztof Kozlowski
2022-07-22 16:50 ` Sean Anderson
0 siblings, 1 reply; 30+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-21 14:42 UTC (permalink / raw)
To: Sean Anderson, Rob Herring
Cc: devicetree, Rob Herring, Russell King, netdev, Paolo Abeni,
Madalin Bucur, Eric Dumazet, David S . Miller,
Krzysztof Kozlowski, Jakub Kicinski, linux-arm-kernel,
linux-kernel
On 17/07/2022 00:47, Sean Anderson wrote:
> On 7/15/22 7:06 PM, Rob Herring wrote:
>> On Fri, 15 Jul 2022 17:59:10 -0400, Sean Anderson wrote:
>>> This converts the MAC portion of the FMan MAC bindings to yaml.
>>>
>>> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
>>> Reviewed-by: Rob Herring <robh@kernel.org>
>>> ---
>>>
>>> Changes in v3:
>>> - Incorporate some minor changes into the first FMan binding commit
>>>
>>> Changes in v2:
>>> - New
>>>
>>> .../bindings/net/fsl,fman-dtsec.yaml | 145 ++++++++++++++++++
>>> .../devicetree/bindings/net/fsl-fman.txt | 128 +---------------
>>> 2 files changed, 146 insertions(+), 127 deletions(-)
>>> create mode 100644 Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
>>>
>>
>> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
>> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>>
>> yamllint warnings/errors:
>>
>> dtschema/dtc warnings/errors:
>> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/fsl,fman-dtsec.example.dtb: ethernet@e8000: 'phy-connection-type', 'phy-handle' do not match any of the regexes: 'pinctrl-[0-9]+'
>> From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
>>
>> doc reference errors (make refcheckdocs):
>
> What's the correct way to do this? I have '$ref: ethernet-controller.yaml#'
> under allOf, but it doesn't seem to apply. IIRC this doesn't occur for actual dts files.
You do not allow any other properties than explicitly listed
(additionalProp:false). If you want to apply all properties from other
schema you need to use unevaluated.
https://elixir.bootlin.com/linux/v5.19-rc7/source/Documentation/devicetree/bindings/writing-bindings.rst#L75
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink
2022-07-21 14:26 ` [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink Camelia Alexandra Groza
@ 2022-07-21 15:39 ` Sean Anderson
0 siblings, 0 replies; 30+ messages in thread
From: Sean Anderson @ 2022-07-21 15:39 UTC (permalink / raw)
To: Camelia Alexandra Groza, David S . Miller, Jakub Kicinski,
Madalin Bucur, netdev@vger.kernel.org
Cc: Paolo Abeni, Eric Dumazet, linux-arm-kernel@lists.infradead.org,
Russell King, linux-kernel@vger.kernel.org, Alexandru Marginean,
Andrew Lunn, Benjamin Herrenschmidt, Heiner Kallweit,
Ioana Ciornei, Jonathan Corbet, Kishon Vijay Abraham I,
Krzysztof Kozlowski, Leo Li, Michael Ellerman, Paul Mackerras,
Rob Herring, Shawn Guo, Vinod Koul, Vladimir Oltean,
devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
linux-phy@lists.infradead.org, linuxppc-dev@lists.ozlabs.org
On 7/21/22 10:26 AM, Camelia Alexandra Groza wrote:
>> -----Original Message-----
>> From: Sean Anderson <sean.anderson@seco.com>
>> Sent: Saturday, July 16, 2022 0:59
>> To: David S . Miller <davem@davemloft.net>; Jakub Kicinski
>> <kuba@kernel.org>; Madalin Bucur <madalin.bucur@nxp.com>;
>> netdev@vger.kernel.org
>> Cc: Paolo Abeni <pabeni@redhat.com>; Eric Dumazet
>> <edumazet@google.com>; linux-arm-kernel@lists.infradead.org; Russell
>> King <linux@armlinux.org.uk>; linux-kernel@vger.kernel.org; Sean Anderson
>> <sean.anderson@seco.com>; Alexandru Marginean
>> <alexandru.marginean@nxp.com>; Andrew Lunn <andrew@lunn.ch>;
>> Benjamin Herrenschmidt <benh@kernel.crashing.org>; Heiner Kallweit
>> <hkallweit1@gmail.com>; Ioana Ciornei <ioana.ciornei@nxp.com>; Jonathan
>> Corbet <corbet@lwn.net>; Kishon Vijay Abraham I <kishon@ti.com>;
>> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Leo Li
>> <leoyang.li@nxp.com>; Michael Ellerman <mpe@ellerman.id.au>; Paul
>> Mackerras <paulus@samba.org>; Rob Herring <robh+dt@kernel.org>;
>> Shawn Guo <shawnguo@kernel.org>; Vinod Koul <vkoul@kernel.org>;
>> Vladimir Oltean <olteanv@gmail.com>; devicetree@vger.kernel.org; linux-
>> doc@vger.kernel.org; linux-phy@lists.infradead.org; linuxppc-
>> dev@lists.ozlabs.org
>> Subject: [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink
>>
>> This series converts the DPAA driver to phylink. Additionally,
>> it also adds a serdes driver to allow for dynamic reconfiguration
>> between 1g and 10g interfaces (such as in an SFP+ slot). These changes
>> are submitted together for this RFT, but they will eventually be
>> submitted separately to the appropriate subsystem maintainers.
>>
>> I have tried to maintain backwards compatibility with existing device
>> trees whereever possible. However, one area where I was unable to
>> achieve this was with QSGMII. Please refer to patch 4 for details.
>>
>> All mac drivers have now been converted. I would greatly appreciate if
>> anyone has QorIQ boards they can test/debug this series on. I only have an
>> LS1046ARDB. Everything but QSGMII should work without breakage; QSGMII
>> needs patches 42 and 43.
>>
>> The serdes driver is mostly functional (except for XFI). This series
>> only adds support for the LS1046ARDB SerDes (and untested LS1088ARDB),
>> but it should be fairly straightforward to add support for other SoCs
>> and boards (see Documentation/driver-api/phy/qoriq.rst).
>>
>> This is the last spin of this series with all patches included. After next
>> week (depending on feedback) I will resend the patches broken up as
>> follows:
>> - 5: 1000BASE-KX support
>> - 1, 6, 44, 45: Lynx 10G support
>> - 7-10, 12-14: Phy rate adaptation support
>> - 2-4, 15-43, 46, 47: DPAA phylink conversion
>
> Please also send patches 15-38 separately from the DPAA1 SerDes and phylink set for easier review
OK.
--Sean
>> Patches 15-19 were first submitted as [1].
>>
>> [1] https://lore.kernel.org/netdev/20220531195851.1592220-1-sean.anderson@seco.com/
>>
>> Changes in v3:
>> - Manually expand yaml references
>> - Add mode configuration to device tree
>> - Expand pcs-handle to an array
>> - Incorperate some minor changes into the first FMan binding commit
>> - Add vendor prefix 'fsl,' to rgmii and mii properties.
>> - Set maxItems for pcs-names
>> - Remove phy-* properties from example because dt-schema complains and
>> I
>> can't be bothered to figure out how to make it work.
>> - Add pcs-handle as a preferred version of pcsphy-handle
>> - Deprecate pcsphy-handle
>> - Remove mii/rmii properties
>> - Add 1000BASE-KX interface mode
>> - Rename remaining references to QorIQ SerDes to Lynx 10G
>> - Fix PLL enable sequence by waiting for our reset request to be cleared
>> before continuing. Do the same for the lock, even though it isn't as
>> critical. Because we will delay for 1.5ms on average, use prepare
>> instead of enable so we can sleep.
>> - Document the status of each protocol
>> - Fix offset of several bitfields in RECR0
>> - Take into account PLLRST_B, SDRST_B, and SDEN when considering whether
>> a PLL is "enabled."
>> - Only power off unused lanes.
>> - Split mode lane mask into first/last lane (like group)
>> - Read modes from device tree
>> - Use caps to determine whether KX/KR are supported
>> - Move modes to lynx_priv
>> - Ensure that the protocol controller is not already in-use when we try
>> to configure a new mode. This should only occur if the device tree is
>> misconfigured (e.g. when QSGMII is selected on two lanes but there is
>> only one QSGMII controller).
>> - Split PLL drivers off into their own file
>> - Add clock for "ext_dly" instead of writing the bit directly (and
>> racing with any clock code).
>> - Use kasprintf instead of open-coding the snprintf dance
>> - Support 1000BASE-KX in lynx_lookup_proto. This still requires PCS
>> support, so nothing is truly "enabled" yet.
>> - Add support for phy rate adaptation
>> - Support differing link speeds and interface speeds
>> - Adjust advertisement based on rate adaptation
>> - Adjust link settings based on rate adaptation
>> - Add support for CRS-based rate adaptation
>> - Add support for AQR115
>> - Add some additional phy interfaces
>> - Add support for aquantia rate adaptation
>> - Put the PCS mdiodev only after we are done with it (since the PCS
>> does not perform a get itself).
>> - Remove _return label from memac_initialization in favor of returning
>> directly
>> - Fix grabbing the default PCS not checking for -ENODATA from
>> of_property_match_string
>> - Set DTSEC_ECNTRL_R100M in dtsec_link_up instead of dtsec_mac_config
>> - Remove rmii/mii properties
>> - Replace 1000Base... with 1000BASE... to match IEEE capitalization
>> - Add compatibles for QSGMII PCSs
>> - Split arm and powerpcs dts updates
>> - Describe modes in device tree
>> - ls1088a: Add serdes bindings
>>
>> Changes in v2:
>> - Rename to fsl,lynx-10g.yaml
>> - Refer to the device in the documentation, rather than the binding
>> - Move compatible first
>> - Document phy cells in the description
>> - Allow a value of 1 for phy-cells. This allows for compatibility with
>> the similar (but according to Ioana Ciornei different enough) lynx-28g
>> binding.
>> - Remove minItems
>> - Use list for clock-names
>> - Fix example binding having too many cells in regs
>> - Add #clock-cells. This will allow using assigned-clocks* to configure
>> the PLLs.
>> - Document the structure of the compatible strings
>> - Convert FMan MAC bindings to yaml
>> - Better document how we select which PCS to use in the default case
>> - Rename driver to Lynx 10G (etc.)
>> - Fix not clearing group->pll after disabling it
>> - Support 1 and 2 phy-cells
>> - Power off lanes during probe
>> - Clear SGMIIaCR1_PCS_EN during probe
>> - Rename LYNX_PROTO_UNKNOWN to LYNX_PROTO_NONE
>> - Handle 1000BASE-KX in lynx_proto_mode_prep
>> - Remove some unused variables
>> - Fix prototype for dtsec_initialization
>> - Fix warning if sizeof(void *) != sizeof(resource_size_t)
>> - Specify type of mac_dev for exception_cb
>> - Add helper for sanity checking cgr ops
>> - Add CGR update function
>> - Adjust queue depth on rate change
>> - Move PCS_LYNX dependency to fman Kconfig
>> - Remove unused variable slow_10g_if
>> - Restrict valid link modes based on the phy interface. This is easier
>> to set up, and mostly captures what I intended to do the first time.
>> We now have a custom validate which restricts half-duplex for some SoCs
>> for RGMII, but generally just uses the default phylink validate.
>> - Configure the SerDes in enable/disable
>> - Properly implement all ethtool ops and ioctls. These were mostly
>> stubbed out just enough to compile last time.
>> - Convert 10GEC and dTSEC as well
>> - Fix capitalization of mEMAC in commit messages
>> - Add nodes for QSGMII PCSs
>> - Add nodes for QSGMII PCSs
>> - Use one phy cell for SerDes1, since no lanes can be grouped
>> - Disable SerDes by default to prevent breaking boards inadvertently.
>>
>> Sean Anderson (47):
>> dt-bindings: phy: Add Lynx 10G phy binding
>> dt-bindings: net: Expand pcs-handle to an array
>> dt-bindings: net: Convert FMan MAC bindings to yaml
>> dt-bindings: net: fman: Add additional interface properties
>> net: phy: Add 1000BASE-KX interface mode
>> [RFT] phy: fsl: Add Lynx 10G SerDes driver
>> net: phy: Add support for rate adaptation
>> net: phylink: Support differing link speeds and interface speeds
>> net: phylink: Adjust advertisement based on rate adaptation
>> net: phylink: Adjust link settings based on rate adaptation
>> [RFC] net: phylink: Add support for CRS-based rate adaptation
>> net: phy: aquantia: Add support for AQR115
>> net: phy: aquantia: Add some additional phy interfaces
>> net: phy: aquantia: Add support for rate adaptation
>> net: fman: Convert to SPDX identifiers
>> net: fman: Don't pass comm_mode to enable/disable
>> net: fman: Store en/disable in mac_device instead of mac_priv_s
>> net: fman: dtsec: Always gracefully stop/start
>> net: fman: Get PCS node in per-mac init
>> net: fman: Store initialization function in match data
>> net: fman: Move struct dev to mac_device
>> net: fman: Configure fixed link in memac_initialization
>> net: fman: Export/rename some common functions
>> net: fman: memac: Use params instead of priv for max_speed
>> net: fman: Move initialization to mac-specific files
>> net: fman: Mark mac methods static
>> net: fman: Inline several functions into initialization
>> net: fman: Remove internal_phy_node from params
>> net: fman: Map the base address once
>> net: fman: Pass params directly to mac init
>> net: fman: Use mac_dev for some params
>> net: fman: Specify type of mac_dev for exception_cb
>> net: fman: Clean up error handling
>> net: fman: Change return type of disable to void
>> net: dpaa: Use mac_dev variable in dpaa_netdev_init
>> soc: fsl: qbman: Add helper for sanity checking cgr ops
>> soc: fsl: qbman: Add CGR update function
>> net: dpaa: Adjust queue depth on rate change
>> net: fman: memac: Add serdes support
>> net: fman: memac: Use lynx pcs driver
>> [RFT] net: dpaa: Convert to phylink
>> powerpc: dts: qoriq: Add nodes for QSGMII PCSs
>> arm64: dts: layerscape: Add nodes for QSGMII PCSs
>> arm64: dts: ls1046a: Add serdes bindings
>> arm64: dts: ls1088a: Add serdes bindings
>> arm64: dts: ls1046ardb: Add serdes bindings
>> [WIP] arm64: dts: ls1088ardb: Add serdes bindings
>>
>> .../bindings/net/dsa/renesas,rzn1-a5psw.yaml | 1 +
>> .../bindings/net/ethernet-controller.yaml | 10 +-
>> .../bindings/net/fsl,fman-dtsec.yaml | 172 +++
>> .../bindings/net/fsl,qoriq-mc-dpmac.yaml | 2 +-
>> .../devicetree/bindings/net/fsl-fman.txt | 133 +-
>> .../devicetree/bindings/phy/fsl,lynx-10g.yaml | 311 ++++
>> Documentation/driver-api/phy/index.rst | 1 +
>> Documentation/driver-api/phy/lynx_10g.rst | 73 +
>> MAINTAINERS | 6 +
>> .../boot/dts/freescale/fsl-ls1043-post.dtsi | 24 +
>> .../boot/dts/freescale/fsl-ls1046-post.dtsi | 25 +
>> .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 34 +
>> .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 179 +++
>> .../boot/dts/freescale/fsl-ls1088a-rdb.dts | 87 ++
>> .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 96 ++
>> .../fsl/qoriq-fman3-0-10g-0-best-effort.dtsi | 3 +-
>> .../boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi | 10 +-
>> .../fsl/qoriq-fman3-0-10g-1-best-effort.dtsi | 10 +-
>> .../boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi | 10 +-
>> .../boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi | 3 +-
>> .../boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi | 10 +-
>> .../boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi | 10 +-
>> .../boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi | 10 +-
>> .../boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi | 3 +-
>> .../boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi | 10 +-
>> .../boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi | 10 +-
>> .../boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi | 10 +-
>> .../boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi | 3 +-
>> .../boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi | 10 +-
>> .../boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi | 10 +-
>> .../boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi | 10 +-
>> .../boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi | 3 +-
>> .../boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi | 10 +-
>> drivers/net/ethernet/freescale/dpaa/Kconfig | 4 +-
>> .../net/ethernet/freescale/dpaa/dpaa_eth.c | 132 +-
>> .../ethernet/freescale/dpaa/dpaa_eth_sysfs.c | 2 +-
>> .../ethernet/freescale/dpaa/dpaa_ethtool.c | 90 +-
>> drivers/net/ethernet/freescale/fman/Kconfig | 4 +-
>> drivers/net/ethernet/freescale/fman/fman.c | 31 +-
>> drivers/net/ethernet/freescale/fman/fman.h | 31 +-
>> .../net/ethernet/freescale/fman/fman_dtsec.c | 674 ++++-----
>> .../net/ethernet/freescale/fman/fman_dtsec.h | 58 +-
>> .../net/ethernet/freescale/fman/fman_keygen.c | 29 +-
>> .../net/ethernet/freescale/fman/fman_keygen.h | 29 +-
>> .../net/ethernet/freescale/fman/fman_mac.h | 34 +-
>> .../net/ethernet/freescale/fman/fman_memac.c | 864 +++++------
>> .../net/ethernet/freescale/fman/fman_memac.h | 57 +-
>> .../net/ethernet/freescale/fman/fman_muram.c | 31 +-
>> .../net/ethernet/freescale/fman/fman_muram.h | 32 +-
>> .../net/ethernet/freescale/fman/fman_port.c | 29 +-
>> .../net/ethernet/freescale/fman/fman_port.h | 29 +-
>> drivers/net/ethernet/freescale/fman/fman_sp.c | 29 +-
>> drivers/net/ethernet/freescale/fman/fman_sp.h | 28 +-
>> .../net/ethernet/freescale/fman/fman_tgec.c | 274 ++--
>> .../net/ethernet/freescale/fman/fman_tgec.h | 54 +-
>> drivers/net/ethernet/freescale/fman/mac.c | 653 +--------
>> drivers/net/ethernet/freescale/fman/mac.h | 66 +-
>> drivers/net/phy/aquantia_main.c | 86 +-
>> drivers/net/phy/phy.c | 21 +
>> drivers/net/phy/phylink.c | 161 +-
>> drivers/phy/freescale/Kconfig | 20 +
>> drivers/phy/freescale/Makefile | 3 +
>> drivers/phy/freescale/lynx-10g.h | 36 +
>> drivers/phy/freescale/phy-fsl-lynx-10g-clk.c | 438 ++++++
>> drivers/phy/freescale/phy-fsl-lynx-10g.c | 1297 +++++++++++++++++
>> drivers/soc/fsl/qbman/qman.c | 76 +-
>> include/linux/phy.h | 42 +
>> include/linux/phylink.h | 12 +-
>> include/soc/fsl/qman.h | 9 +
>> 69 files changed, 4408 insertions(+), 2356 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/net/fsl,fman-
>> dtsec.yaml
>> create mode 100644 Documentation/devicetree/bindings/phy/fsl,lynx-
>> 10g.yaml
>> create mode 100644 Documentation/driver-api/phy/lynx_10g.rst
>> create mode 100644 drivers/phy/freescale/lynx-10g.h
>> create mode 100644 drivers/phy/freescale/phy-fsl-lynx-10g-clk.c
>> create mode 100644 drivers/phy/freescale/phy-fsl-lynx-10g.c
>>
>> --
>> 2.35.1.1320.gc452695387.dirty
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes bindings
2022-07-21 14:20 ` Camelia Alexandra Groza
@ 2022-07-21 15:40 ` Sean Anderson
2022-07-22 12:41 ` Camelia Alexandra Groza
0 siblings, 1 reply; 30+ messages in thread
From: Sean Anderson @ 2022-07-21 15:40 UTC (permalink / raw)
To: Camelia Alexandra Groza, David S . Miller, Jakub Kicinski,
Madalin Bucur, netdev@vger.kernel.org
Cc: Paolo Abeni, Eric Dumazet, linux-arm-kernel@lists.infradead.org,
Russell King, linux-kernel@vger.kernel.org,
Kishon Vijay Abraham I, Krzysztof Kozlowski, Leo Li, Rob Herring,
Shawn Guo, Vinod Koul, devicetree@vger.kernel.org,
linux-phy@lists.infradead.org
On 7/21/22 10:20 AM, Camelia Alexandra Groza wrote:
>> -----Original Message-----
>> From: Sean Anderson <sean.anderson@seco.com>
>> Sent: Saturday, July 16, 2022 1:00
>> To: David S . Miller <davem@davemloft.net>; Jakub Kicinski
>> <kuba@kernel.org>; Madalin Bucur <madalin.bucur@nxp.com>;
>> netdev@vger.kernel.org
>> Cc: Paolo Abeni <pabeni@redhat.com>; Eric Dumazet
>> <edumazet@google.com>; linux-arm-kernel@lists.infradead.org; Russell
>> King <linux@armlinux.org.uk>; linux-kernel@vger.kernel.org; Sean Anderson
>> <sean.anderson@seco.com>; Kishon Vijay Abraham I <kishon@ti.com>;
>> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Leo Li
>> <leoyang.li@nxp.com>; Rob Herring <robh+dt@kernel.org>; Shawn Guo
>> <shawnguo@kernel.org>; Vinod Koul <vkoul@kernel.org>;
>> devicetree@vger.kernel.org; linux-phy@lists.infradead.org
>> Subject: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes
>> bindings
>>
>> This adds appropriate bindings for the macs which use the SerDes. The
>> 156.25MHz fixed clock is a crystal. The 100MHz clocks (there are
>> actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is
>> no driver for this device (and as far as I know all you can do with the
>> 100MHz clocks is gate them), so I have chosen to model it as a single
>> fixed clock.
>>
>> Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
>> This means that Lane A (what the driver thinks is lane 0) uses pins
>> SD1_TX3_P/N.
>>
>> Because this will break ethernet if the serdes is not enabled, enable
>> the serdes driver by default on Layerscape.
>>
>> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
>> ---
>> Please let me know if there is a better/more specific config I can use
>> here.
>>
>> (no changes since v1)
>
> My LS1046ARDB hangs at boot with this patch right after the second SerDes is probed,
> right before the point where the PCI host bridge is registered. I can get around this
> either by disabling the second SerDes node from the device tree, or disabling
> CONFIG_PCI_LAYERSCAPE at build.
>
> I haven't debugged it more but there seems to be an issue here.
Hm. Do you have anything plugged into the PCIe/SATA slots? I haven't been testing with
anything there. For now, it may be better to just leave it disabled.
--Sean
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH net-next v3 01/47] dt-bindings: phy: Add Lynx 10G phy binding
2022-07-20 22:17 ` Rob Herring
@ 2022-07-21 16:05 ` Sean Anderson
2022-07-21 18:29 ` Rob Herring
0 siblings, 1 reply; 30+ messages in thread
From: Sean Anderson @ 2022-07-21 16:05 UTC (permalink / raw)
To: Rob Herring
Cc: David S . Miller, Jakub Kicinski, Madalin Bucur, netdev,
Paolo Abeni, Eric Dumazet, linux-arm-kernel, Russell King,
linux-kernel, Kishon Vijay Abraham I, Krzysztof Kozlowski,
Vinod Koul, devicetree, linux-phy
On 7/20/22 6:17 PM, Rob Herring wrote:
> On Fri, Jul 15, 2022 at 05:59:08PM -0400, Sean Anderson wrote:
>> This adds a binding for the SerDes module found on QorIQ processors. The
>> phy reference has two cells, one for the first lane and one for the
>> last. This should allow for good support of multi-lane protocols when
>> (if) they are added. There is no protocol option, because the driver is
>> designed to be able to completely reconfigure lanes at runtime.
>> Generally, the phy consumer can select the appropriate protocol using
>> set_mode. For the most part there is only one protocol controller
>> (consumer) per lane/protocol combination. The exception to this is the
>> B4860 processor, which has some lanes which can be connected to
>> multiple MACs. For that processor, I anticipate the easiest way to
>> resolve this will be to add an additional cell with a "protocol
>> controller instance" property.
>>
>> Each serdes has a unique set of supported protocols (and lanes). The
>> support matrix is configured in the device tree. The format of each
>> PCCR (protocol configuration register) is modeled. Although the general
>> format is typically the same across different SoCs, the specific
>> supported protocols (and the values necessary to select them) are
>> particular to individual SerDes. A nested structure is used to reduce
>> duplication of data.
>>
>> There are two PLLs, each of which can be used as the master clock for
>> each lane. Each PLL has its own reference. For the moment they are
>> required, because it simplifies the driver implementation. Absent
>> reference clocks can be modeled by a fixed-clock with a rate of 0.
>>
>> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
>> ---
>>
>> Changes in v3:
>> - Manually expand yaml references
>> - Add mode configuration to device tree
>>
>> Changes in v2:
>> - Rename to fsl,lynx-10g.yaml
>> - Refer to the device in the documentation, rather than the binding
>> - Move compatible first
>> - Document phy cells in the description
>> - Allow a value of 1 for phy-cells. This allows for compatibility with
>> the similar (but according to Ioana Ciornei different enough) lynx-28g
>> binding.
>> - Remove minItems
>> - Use list for clock-names
>> - Fix example binding having too many cells in regs
>> - Add #clock-cells. This will allow using assigned-clocks* to configure
>> the PLLs.
>> - Document the structure of the compatible strings
>>
>> .../devicetree/bindings/phy/fsl,lynx-10g.yaml | 311 ++++++++++++++++++
>> 1 file changed, 311 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
>> new file mode 100644
>> index 000000000000..a2c37225bb67
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
>> @@ -0,0 +1,311 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/phy/fsl,lynx-10g.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: NXP Lynx 10G SerDes
>> +
>> +maintainers:
>> + - Sean Anderson <sean.anderson@seco.com>
>> +
>> +description: |
>> + These Lynx "SerDes" devices are found in NXP's QorIQ line of processors. The
>> + SerDes provides up to eight lanes. Each lane may be configured individually,
>> + or may be combined with adjacent lanes for a multi-lane protocol. The SerDes
>> + supports a variety of protocols, including up to 10G Ethernet, PCIe, SATA, and
>> + others. The specific protocols supported for each lane depend on the
>> + particular SoC.
>> +
>> +definitions:
>
> $defs:
That didn't work until recently :)
I will change this for next revision.
>> + fsl,cfg:
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + minimum: 1
>> + description: |
>> + The configuration value to program into the field.
>
> What field?
Ah, looks like this lost some context when I moved it. I will expand on this.
>> +
>> + fsl,first-lane:
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + minimum: 0
>> + maximum: 7
>> + description: |
>> + The first lane in the group configured by fsl,cfg. This lane will have
>> + the FIRST_LANE bit set in GCR0. The reset direction will also be set
>> + based on whether this property is less than or greater than
>> + fsl,last-lane.
>> +
>> + fsl,last-lane:
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + minimum: 0
>> + maximum: 7
>> + description: |
>> + The last lane configured by fsl,cfg. If this property is absent,
>> + then it will default to the value of fsl,first-lane.
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - enum:
>> + - fsl,ls1046a-serdes
>> + - fsl,ls1088a-serdes
>> + - const: fsl,lynx-10g
>> +
>> + "#clock-cells":
>> + const: 1
>> + description: |
>> + The cell contains the index of the PLL, starting from 0. Note that when
>> + assigning a rate to a PLL, the PLLs' rates are divided by 1000 to avoid
>> + overflow. A rate of 5000000 corresponds to 5GHz.
>> +
>> + "#phy-cells":
>> + minimum: 1
>> + maximum: 2
>> + description: |
>> + The cells contain the following arguments:
>> + - The first lane in the group. Lanes are numbered based on the register
>> + offsets, not the I/O ports. This corresponds to the letter-based ("Lane
>> + A") naming scheme, and not the number-based ("Lane 0") naming scheme. On
>> + most SoCs, "Lane A" is "Lane 0", but not always.
>> + - Last lane. For single-lane protocols, this should be the same as the
>> + first lane.
>
> Perhaps a single cell with a lane mask would be simpler.
Yes.
>> + If no lanes in a SerDes can be grouped, then #phy-cells may be 1, and the
>> + first cell will specify the only lane in the group.
>
> It is generally easier to have a fixed number of cells.
This was remarked on last time. I allowed this for better compatibility with the lynx
28g serdes binding. Is that reasonable? I agree it would simplify the driver to just
have one cell type.
>> +
>> + clocks:
>> + maxItems: 2
>> + description: |
>> + Clock for each PLL reference clock input.
>> +
>> + clock-names:
>> + minItems: 2
>> + maxItems: 2
>> + items:
>> + enum:
>> + - ref0
>> + - ref1
>> +
>> + reg:
>> + maxItems: 1
>> +
>> +patternProperties:
>> + '^pccr-':
>> + type: object
>> +
>> + description: |
>> + One of the protocol configuration registers (PCCRs). These contains
>> + several fields, each of which mux a particular protocol onto a particular
>> + lane.
>> +
>> + properties:
>> + fsl,pccr:
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + description: |
>> + The index of the PCCR. This is the same as the register name suffix.
>> + For example, a node for PCCRB would use a value of '0xb' for an
>> + offset of 0x22C (0x200 + 4 * 0xb).
>> +
>> + patternProperties:
>> + '^(q?sgmii|xfi|pcie|sata)-':
>> + type: object
>> +
>> + description: |
>> + A configuration field within a PCCR. Each field configures one
>> + protocol controller. The value of the field determines the lanes the
>> + controller is connected to, if any.
>> +
>> + properties:
>> + fsl,index:
>
> indexes are generally a red flag in binding. What is the index, how does
> it correspond to the h/w and why do you need it.
As described in the description below, the "index" is the protocol controller suffix,
corresponding to a particular field (or set of fields) in the protocol configuration
registers.
> If we do end up needing
> it, 'reg' is generally how we address some component.
I originally used reg, but I got warnings about inheriting #size-cells and
#address-cells. These bindings are already quite verbose to write out (there
are around 10-20 configurations per SerDes to describe) and I would like to
minimize the amount of properties to what is necessary. Additionally, this
really describes a particular index of a field, and not a register (or an offset
within a register).
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + description: |
>> + The index of the field. This corresponds to the suffix in the
>
> What field?
The one from the description above.
>> + documentation. For example, PEXa would be 0, PEXb 1, etc.
>> + Generally, higher fields occupy lower bits.
>> +
>> + If there are any subnodes present, they will be preferred over
>> + fsl,cfg et. al.
>> +
>> + fsl,cfg:
>> + $ref: "#/definitions/fsl,cfg"
>> +
>> + fsl,first-lane:
>> + $ref: "#/definitions/fsl,first-lane"
>> +
>> + fsl,last-lane:
>> + $ref: "#/definitions/fsl,last-lane"
>
> Why do you have lane assignments here and in the phy cells?
For three reasons. First, because we need to know what protocols are valid on what
lanes. The idea is to allow the MAC to configure the protocols at runtime. To do
this, someone has to figure out if the protocol is supported on that lane. The
best place to put this IMO is the serdes.
Second, some serdes have (mostly) unsupported protocols such as PCIe as well as
Ethernet protocols. To allow using Ethernet, we need to know which lanes are
configured (by the firmware/bootloader) for some other protocol. That way, we
can avoid touching them.
Third, as part of the probe sequence, we need to ensure that no protocol controllers
are currently selected. Otherwise, we will get strange problems later when we try
to connect multiple protocol controllers to the same lane.
>> +
>> + fsl,proto:
>> + $ref: /schemas/types.yaml#/definitions/string
>> + enum:
>> + - sgmii
>> + - sgmii25
>> + - qsgmii
>> + - xfi
>> + - pcie
>> + - sata
>
> We have standard phy modes already for at least most of these types.
> Generally the mode is set in the phy cells.
Yes, but this is the "protocol" which may correspond to multiple phy modes.
For example, sgmii25 allows SGMII, 1000BASE-X, 1000BASE-KR, and 2500BASE-X
phy modes.
>> + description: |
>> + Indicates the basic group protocols supported by this field.
>> + Individual protocols are selected by configuring the protocol
>> + controller.
>> +
>> + - sgmii: 1000BASE-X, SGMII, and 1000BASE-KX (depending on the
>> + SoC)
>> + - sgmii25: 2500BASE-X, 1000BASE-X, SGMII, and 1000BASE-KX
>> + (depending on the SoC)
>> + - qsgmii: QSGMII
>> + - xfi: 10GBASE-R and 10GBASE-KR (depending on the SoC)
>> + - pcie: PCIe
>> + - sata: SATA
>> +
>> + patternProperties:
>> + '^cfg-':
>> + type: object
>> +
>> + description: |
>> + A single field may have multiple values which, when programmed,
>> + connect the protocol controller to different lanes. If this is the
>> + case, multiple sub-nodes may be provided, each describing a
>> + single muxing.
>> +
>> + properties:
>> + fsl,cfg:
>> + $ref: "#/definitions/fsl,cfg"
>> +
>> + fsl,first-lane:
>> + $ref: "#/definitions/fsl,first-lane"
>> +
>> + fsl,last-lane:
>> + $ref: "#/definitions/fsl,last-lane"
>> +
>> + required:
>> + - fsl,cfg
>> + - fsl,first-lane
>> +
>> + dependencies:
>> + fsl,last-lane:
>> + - fsl,first-lane
>> +
>> + additionalProperties: false
>> +
>> + required:
>> + - fsl,index
>> + - fsl,proto
>> +
>> + dependencies:
>> + fsl,last-lane:
>> + - fsl,first-lane
>> + fsl,cfg:
>> + - fsl,first-lane
>> + fsl,first-lane:
>> + - fsl,cfg
>> +
>> + # I would like to require either a config subnode or the config
>> + # properties (and not both), but from what I can tell that can't be
>> + # expressed in json schema. In particular, it is not possible to
>> + # require a pattern property.
>
> Indeed, it is not. There's been some proposals.
>
>> +
>> + additionalProperties: false
>> +
>> + required:
>> + - fsl,pccr
>> +
>> + additionalProperties: false
>> +
>> +required:
>> + - "#clock-cells"
>> + - "#phy-cells"
>> + - compatible
>> + - clocks
>> + - clock-names
>> + - reg
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + serdes1: phy@1ea0000 {
>> + #clock-cells = <1>;
>> + #phy-cells = <2>;
>> + compatible = "fsl,ls1088a-serdes", "fsl,lynx-10g";
>> + reg = <0x1ea0000 0x2000>;
>> + clocks = <&clk_100mhz>, <&clk_156_mhz>;
>> + clock-names = "ref0", "ref1";
>> + assigned-clocks = <&serdes1 0>;
>> + assigned-clock-rates = <5000000>;
>> +
>> + pccr-8 {
>> + fsl,pccr = <0x8>;
>> +
>> + sgmii-0 {
>> + fsl,index = <0>;
>> + fsl,cfg = <0x1>;
>> + fsl,first-lane = <3>;
>> + fsl,proto = "sgmii";
>> + };
>> +
>> + sgmii-1 {
>> + fsl,index = <1>;
>> + fsl,cfg = <0x1>;
>> + fsl,first-lane = <2>;
>> + fsl,proto = "sgmii";
>> + };
>> +
>> + sgmii-2 {
>> + fsl,index = <2>;
>> + fsl,cfg = <0x1>;
>> + fsl,first-lane = <1>;
>> + fsl,proto = "sgmii25";
>> + };
>> +
>> + sgmii-3 {
>> + fsl,index = <3>;
>> + fsl,cfg = <0x1>;
>> + fsl,first-lane = <0>;
>> + fsl,proto = "sgmii25";
>> + };
>> + };
>> +
>> + pccr-9 {
>> + fsl,pccr = <0x9>;
>> +
>> + qsgmii-0 {
>> + fsl,index = <0>;
>> + fsl,cfg = <0x1>;
>> + fsl,first-lane = <3>;
>> + fsl,proto = "qsgmii";
>> + };
>> +
>> + qsgmii-1 {
>> + fsl,index = <1>;
>> + fsl,proto = "qsgmii";
>> +
>> + cfg-1 {
>> + fsl,cfg = <0x1>;
>> + fsl,first-lane = <2>;
>> + };
>> +
>> + cfg-2 {
>> + fsl,cfg = <0x2>;
>> + fsl,first-lane = <0>;
>> + };
>> + };
>> + };
>> +
>> + pccr-b {
>> + fsl,pccr = <0xb>;
>> +
>> + xfi-0 {
>> + fsl,index = <0>;
>> + fsl,cfg = <0x1>;
>> + fsl,first-lane = <1>;
>> + fsl,proto = "xfi";
>> + };
>> +
>> + xfi-1 {
>> + fsl,index = <1>;
>> + fsl,cfg = <0x1>;
>> + fsl,first-lane = <0>;
>> + fsl,proto = "xfi";
>> + };
>> + };
>> + };
>
> Other than lane assignments and modes, I don't really understand what
> you are trying to do.
This is touched on a bit above, but the idea here is to allow for dynamic
reconfiguration of the serdes mode in order to support multiple ethernet
phy modes at runtime. To do this, we need to know about all the available
protocol controllers, and the lanes they support. In particular, the
available controllers and the lanes they map to (and the values to
program to select them) differ even between different serdes on the same
SoC.
> It all looks too complex and I don't see any other
> phy bindings needing something this complex.
This was explicitly asked for last time. I also would not like to do this,
but you and Krzysztof Kozlowski were very opposed to having per-device
compatible strings. If you have a suggestion for a different approach, I
am all ears. I find it very frustrating that the primary feedback I get from
the device tree folks is "you can't do this" without a corresponding "do it
this way."
--Sean
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH net-next v3 42/47] powerpc: dts: qoriq: Add nodes for QSGMII PCSs
2022-07-21 13:48 ` Camelia Alexandra Groza
@ 2022-07-21 17:51 ` Sean Anderson
0 siblings, 0 replies; 30+ messages in thread
From: Sean Anderson @ 2022-07-21 17:51 UTC (permalink / raw)
To: Camelia Alexandra Groza, David S . Miller, Jakub Kicinski,
Madalin Bucur, netdev@vger.kernel.org
Cc: devicetree@vger.kernel.org, Leo Li, linuxppc-dev@lists.ozlabs.org,
Russell King, linux-kernel@vger.kernel.org, Eric Dumazet,
Rob Herring, Paul Mackerras, Krzysztof Kozlowski, Paolo Abeni,
Shawn Guo, linux-arm-kernel@lists.infradead.org
On 7/21/22 9:48 AM, Camelia Alexandra Groza wrote:
>> -----Original Message-----
>> From: Linuxppc-dev <linuxppc-dev-
>> bounces+camelia.groza=nxp.com@lists.ozlabs.org> On Behalf Of Sean
>> Anderson
>> Sent: Saturday, July 16, 2022 1:00
>> To: David S . Miller <davem@davemloft.net>; Jakub Kicinski
>> <kuba@kernel.org>; Madalin Bucur <madalin.bucur@nxp.com>;
>> netdev@vger.kernel.org
>> Cc: devicetree@vger.kernel.org; Leo Li <leoyang.li@nxp.com>; Sean
>> Anderson <sean.anderson@seco.com>; linuxppc-dev@lists.ozlabs.org;
>> Russell King <linux@armlinux.org.uk>; linux-kernel@vger.kernel.org; Eric
>> Dumazet <edumazet@google.com>; Rob Herring <robh+dt@kernel.org>;
>> Paul Mackerras <paulus@samba.org>; Krzysztof Kozlowski
>> <krzysztof.kozlowski+dt@linaro.org>; Paolo Abeni <pabeni@redhat.com>;
>> Shawn Guo <shawnguo@kernel.org>; linux-arm-kernel@lists.infradead.org
>> Subject: [PATCH net-next v3 42/47] powerpc: dts: qoriq: Add nodes for
>> QSGMII PCSs
>>
>> Now that we actually read registers from QSGMII PCSs, it's important
>> that we have the correct address (instead of hoping that we're the MAC
>> with all the QSGMII PCSs on its bus). This adds nodes for the QSGMII
>> PCSs. They have the same addresses on all SoCs (e.g. if QSGMIIA is
>> present it's used for MACs 1 through 4).
>>
>> Since the first QSGMII PCSs share an address with the SGMII and XFI
>> PCSs, we only add new nodes for PCSs 2-4. This avoids address conflicts
>> on the bus.
>>
>> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
>
> MAC1 and MAC2 can be XFI on T2080. This needs to be reflected in qoriq-fman3-0-1g-0.dtsi
> and qoriq-fman3-0-1g-1.dtsi
>
> The two associated netdevs fail to probe on a T2080RDB without "xfi" added to the pcs-names:
> fsl_dpaa_mac ffe4e0000.ethernet (unnamed net_device) (uninitialized): failed to validate link configuration for in-band status
> fsl_dpaa_mac ffe4e0000.ethernet: error -EINVAL: Could not create phylink
> fsl_dpa: probe of dpaa-ethernet.0 failed with error -22
Ah, I missed that this SoC had 10G on MAC1/MAC2. Going with the existing
naming scheme, these MACs should probably go in DTSs named
qoriq-fman3-0-1g-2.dtsi and qoriq-fman3-0-1g-3.dtsi. Alternatively, this
could be done in t2081si-post.dtsi, since it is only for one SoC. I don't
want to add these to qoriq-fman3-0-1g-0.dtsi and qoriq-fman3-0-1g-1.dtsi
because they are used on other SoCs which don't have 10G.
--Sean
>> ---
>>
>> Changes in v3:
>> - Add compatibles for QSGMII PCSs
>> - Split arm and powerpcs dts updates
>>
>> Changes in v2:
>> - New
>>
>> .../boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi | 3 ++-
>> arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi | 10 +++++++++-
>> .../boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi | 10 +++++++++-
>> arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi | 10 +++++++++-
>> arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi | 3 ++-
>> arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi | 10 +++++++++-
>> arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi | 10 +++++++++-
>> arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi | 10 +++++++++-
>> arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi | 3 ++-
>> arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi | 10 +++++++++-
>> arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi | 10 +++++++++-
>> arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi | 10 +++++++++-
>> arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi | 3 ++-
>> arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi | 10 +++++++++-
>> arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi | 10 +++++++++-
>> arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi | 10 +++++++++-
>> arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi | 3 ++-
>> arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi | 10 +++++++++-
>> 18 files changed, 127 insertions(+), 18 deletions(-)
>>
>> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
>> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
>> index baa0c503e741..db169d630db3 100644
>> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
>> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
>> @@ -55,7 +55,8 @@ ethernet@e0000 {
>> reg = <0xe0000 0x1000>;
>> fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
>> ptp-timer = <&ptp_timer0>;
>> - pcsphy-handle = <&pcsphy0>;
>> + pcsphy-handle = <&pcsphy0>, <&pcsphy0>;
>> + pcs-names = "sgmii", "qsgmii";
>> };
>>
>> mdio@e1000 {
>> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
>> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
>> index 93095600e808..e80ad8675be8 100644
>> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
>> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
>> @@ -52,7 +52,15 @@ ethernet@f0000 {
>> compatible = "fsl,fman-memac";
>> reg = <0xf0000 0x1000>;
>> fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
>> - pcsphy-handle = <&pcsphy6>;
>> + pcsphy-handle = <&pcsphy6>, <&qsgmiib_pcs2>,
>> <&pcsphy6>;
>> + pcs-names = "sgmii", "qsgmii", "xfi";
>> + };
>> +
>> + mdio@e9000 {
>> + qsgmiib_pcs2: ethernet-pcs@2 {
>> + compatible = "fsl,lynx-pcs";
>> + reg = <2>;
>> + };
>> };
>>
>> mdio@f1000 {
>> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
>> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
>> index ff4bd38f0645..6a6f51842ad5 100644
>> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
>> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
>> @@ -55,7 +55,15 @@ ethernet@e2000 {
>> reg = <0xe2000 0x1000>;
>> fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
>> ptp-timer = <&ptp_timer0>;
>> - pcsphy-handle = <&pcsphy1>;
>> + pcsphy-handle = <&pcsphy1>, <&qsgmiia_pcs1>;
>> + pcs-names = "sgmii", "qsgmii";
>> + };
>> +
>> + mdio@e1000 {
>> + qsgmiia_pcs1: ethernet-pcs@1 {
>> + compatible = "fsl,lynx-pcs";
>> + reg = <1>;
>> + };
>> };
>>
>> mdio@e3000 {
>> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
>> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
>> index 1fa38ed6f59e..543da5493e40 100644
>> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
>> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
>> @@ -52,7 +52,15 @@ ethernet@f2000 {
>> compatible = "fsl,fman-memac";
>> reg = <0xf2000 0x1000>;
>> fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
>> - pcsphy-handle = <&pcsphy7>;
>> + pcsphy-handle = <&pcsphy7>, <&qsgmiib_pcs3>,
>> <&pcsphy7>;
>> + pcs-names = "sgmii", "qsgmii", "xfi";
>> + };
>> +
>> + mdio@e9000 {
>> + qsgmiib_pcs3: ethernet-pcs@3 {
>> + compatible = "fsl,lynx-pcs";
>> + reg = <3>;
>> + };
>> };
>>
>> mdio@f3000 {
>> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi
>> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi
>> index a8cc9780c0c4..ce76725e6eb2 100644
>> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi
>> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi
>> @@ -51,7 +51,8 @@ ethernet@e0000 {
>> reg = <0xe0000 0x1000>;
>> fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
>> ptp-timer = <&ptp_timer0>;
>> - pcsphy-handle = <&pcsphy0>;
>> + pcsphy-handle = <&pcsphy0>, <&pcsphy0>;
>> + pcs-names = "sgmii", "qsgmii";
>> };
>>
>> mdio@e1000 {
>> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi
>> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi
>> index 8b8bd70c9382..f3af67df4767 100644
>> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi
>> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi
>> @@ -51,7 +51,15 @@ ethernet@e2000 {
>> reg = <0xe2000 0x1000>;
>> fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
>> ptp-timer = <&ptp_timer0>;
>> - pcsphy-handle = <&pcsphy1>;
>> + pcsphy-handle = <&pcsphy1>, <&qsgmiia_pcs1>;
>> + pcs-names = "sgmii", "qsgmii";
>> + };
>> +
>> + mdio@e1000 {
>> + qsgmiia_pcs1: ethernet-pcs@1 {
>> + compatible = "fsl,lynx-pcs";
>> + reg = <1>;
>> + };
>> };
>>
>> mdio@e3000 {
>> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi
>> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi
>> index 619c880b54d8..f6d74de84bfe 100644
>> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi
>> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi
>> @@ -51,7 +51,15 @@ ethernet@e4000 {
>> reg = <0xe4000 0x1000>;
>> fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
>> ptp-timer = <&ptp_timer0>;
>> - pcsphy-handle = <&pcsphy2>;
>> + pcsphy-handle = <&pcsphy2>, <&qsgmiia_pcs2>;
>> + pcs-names = "sgmii", "qsgmii";
>> + };
>> +
>> + mdio@e1000 {
>> + qsgmiia_pcs2: ethernet-pcs@2 {
>> + compatible = "fsl,lynx-pcs";
>> + reg = <2>;
>> + };
>> };
>>
>> mdio@e5000 {
>> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi
>> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi
>> index d7ebb73a400d..6e091d8ae9e2 100644
>> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi
>> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi
>> @@ -51,7 +51,15 @@ ethernet@e6000 {
>> reg = <0xe6000 0x1000>;
>> fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
>> ptp-timer = <&ptp_timer0>;
>> - pcsphy-handle = <&pcsphy3>;
>> + pcsphy-handle = <&pcsphy3>, <&qsgmiia_pcs3>;
>> + pcs-names = "sgmii", "qsgmii";
>> + };
>> +
>> + mdio@e1000 {
>> + qsgmiia_pcs3: ethernet-pcs@3 {
>> + compatible = "fsl,lynx-pcs";
>> + reg = <3>;
>> + };
>> };
>>
>> mdio@e7000 {
>> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi
>> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi
>> index b151d696a069..e2174c0fc841 100644
>> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi
>> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi
>> @@ -51,7 +51,8 @@ ethernet@e8000 {
>> reg = <0xe8000 0x1000>;
>> fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
>> ptp-timer = <&ptp_timer0>;
>> - pcsphy-handle = <&pcsphy4>;
>> + pcsphy-handle = <&pcsphy4>, <&pcsphy4>;
>> + pcs-names = "sgmii", "qsgmii";
>> };
>>
>> mdio@e9000 {
>> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi
>> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi
>> index adc0ae0013a3..9106815bd63e 100644
>> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi
>> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi
>> @@ -51,7 +51,15 @@ ethernet@ea000 {
>> reg = <0xea000 0x1000>;
>> fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
>> ptp-timer = <&ptp_timer0>;
>> - pcsphy-handle = <&pcsphy5>;
>> + pcsphy-handle = <&pcsphy5>, <&qsgmiib_pcs1>;
>> + pcs-names = "sgmii", "qsgmii";
>> + };
>> +
>> + mdio@e9000 {
>> + qsgmiib_pcs1: ethernet-pcs@1 {
>> + compatible = "fsl,lynx-pcs";
>> + reg = <1>;
>> + };
>> };
>>
>> mdio@eb000 {
>> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi
>> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi
>> index 435047e0e250..a3c1538dfda1 100644
>> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi
>> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi
>> @@ -52,7 +52,15 @@ ethernet@f0000 {
>> compatible = "fsl,fman-memac";
>> reg = <0xf0000 0x1000>;
>> fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
>> - pcsphy-handle = <&pcsphy14>;
>> + pcsphy-handle = <&pcsphy14>, <&qsgmiid_pcs2>,
>> <&pcsphy14>;
>> + pcs-names = "sgmii", "qsgmii", "xfi";
>> + };
>> +
>> + mdio@e9000 {
>> + qsgmiid_pcs2: ethernet-pcs@2 {
>> + compatible = "fsl,lynx-pcs";
>> + reg = <2>;
>> + };
>> };
>>
>> mdio@f1000 {
>> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi
>> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi
>> index c098657cca0a..c024517e70d6 100644
>> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi
>> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi
>> @@ -52,7 +52,15 @@ ethernet@f2000 {
>> compatible = "fsl,fman-memac";
>> reg = <0xf2000 0x1000>;
>> fsl,fman-ports = <&fman1_rx_0x11 &fman1_tx_0x31>;
>> - pcsphy-handle = <&pcsphy15>;
>> + pcsphy-handle = <&pcsphy15>, <&qsgmiid_pcs3>,
>> <&pcsphy15>;
>> + pcs-names = "sgmii", "qsgmii", "xfi";
>> + };
>> +
>> + mdio@e9000 {
>> + qsgmiid_pcs3: ethernet-pcs@3 {
>> + compatible = "fsl,lynx-pcs";
>> + reg = <3>;
>> + };
>> };
>>
>> mdio@f3000 {
>> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi
>> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi
>> index 9d06824815f3..16fb299f615a 100644
>> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi
>> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi
>> @@ -51,7 +51,8 @@ ethernet@e0000 {
>> reg = <0xe0000 0x1000>;
>> fsl,fman-ports = <&fman1_rx_0x08 &fman1_tx_0x28>;
>> ptp-timer = <&ptp_timer1>;
>> - pcsphy-handle = <&pcsphy8>;
>> + pcsphy-handle = <&pcsphy8>, <&pcsphy8>;
>> + pcs-names = "sgmii", "qsgmii";
>> };
>>
>> mdio@e1000 {
>> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi
>> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi
>> index 70e947730c4b..75cecbef8469 100644
>> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi
>> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi
>> @@ -51,7 +51,15 @@ ethernet@e2000 {
>> reg = <0xe2000 0x1000>;
>> fsl,fman-ports = <&fman1_rx_0x09 &fman1_tx_0x29>;
>> ptp-timer = <&ptp_timer1>;
>> - pcsphy-handle = <&pcsphy9>;
>> + pcsphy-handle = <&pcsphy9>, <&qsgmiic_pcs1>;
>> + pcs-names = "sgmii", "qsgmii";
>> + };
>> +
>> + mdio@e1000 {
>> + qsgmiic_pcs1: ethernet-pcs@1 {
>> + compatible = "fsl,lynx-pcs";
>> + reg = <1>;
>> + };
>> };
>>
>> mdio@e3000 {
>> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi
>> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi
>> index ad96e6529595..98c1d27f17e7 100644
>> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi
>> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi
>> @@ -51,7 +51,15 @@ ethernet@e4000 {
>> reg = <0xe4000 0x1000>;
>> fsl,fman-ports = <&fman1_rx_0x0a &fman1_tx_0x2a>;
>> ptp-timer = <&ptp_timer1>;
>> - pcsphy-handle = <&pcsphy10>;
>> + pcsphy-handle = <&pcsphy10>, <&qsgmiic_pcs2>;
>> + pcs-names = "sgmii", "qsgmii";
>> + };
>> +
>> + mdio@e1000 {
>> + qsgmiic_pcs2: ethernet-pcs@2 {
>> + compatible = "fsl,lynx-pcs";
>> + reg = <2>;
>> + };
>> };
>>
>> mdio@e5000 {
>> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi
>> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi
>> index 034bc4b71f7a..203a00036f17 100644
>> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi
>> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi
>> @@ -51,7 +51,15 @@ ethernet@e6000 {
>> reg = <0xe6000 0x1000>;
>> fsl,fman-ports = <&fman1_rx_0x0b &fman1_tx_0x2b>;
>> ptp-timer = <&ptp_timer1>;
>> - pcsphy-handle = <&pcsphy11>;
>> + pcsphy-handle = <&pcsphy11>, <&qsgmiic_pcs3>;
>> + pcs-names = "sgmii", "qsgmii";
>> + };
>> +
>> + mdio@e1000 {
>> + qsgmiic_pcs3: ethernet-pcs@3 {
>> + compatible = "fsl,lynx-pcs";
>> + reg = <3>;
>> + };
>> };
>>
>> mdio@e7000 {
>> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi
>> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi
>> index 93ca23d82b39..9366935ebc02 100644
>> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi
>> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi
>> @@ -51,7 +51,8 @@ ethernet@e8000 {
>> reg = <0xe8000 0x1000>;
>> fsl,fman-ports = <&fman1_rx_0x0c &fman1_tx_0x2c>;
>> ptp-timer = <&ptp_timer1>;
>> - pcsphy-handle = <&pcsphy12>;
>> + pcsphy-handle = <&pcsphy12>, <&pcsphy12>;
>> + pcs-names = "sgmii", "qsgmii";
>> };
>>
>> mdio@e9000 {
>> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi
>> b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi
>> index 23b3117a2fd2..39f7c6133017 100644
>> --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi
>> +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi
>> @@ -51,7 +51,15 @@ ethernet@ea000 {
>> reg = <0xea000 0x1000>;
>> fsl,fman-ports = <&fman1_rx_0x0d &fman1_tx_0x2d>;
>> ptp-timer = <&ptp_timer1>;
>> - pcsphy-handle = <&pcsphy13>;
>> + pcsphy-handle = <&pcsphy13>, <&qsgmiid_pcs1>;
>> + pcs-names = "sgmii", "qsgmii";
>> + };
>> +
>> + mdio@e9000 {
>> + qsgmiid_pcs1: ethernet-pcs@1 {
>> + compatible = "fsl,lynx-pcs";
>> + reg = <1>;
>> + };
>> };
>>
>> mdio@eb000 {
>> --
>> 2.35.1.1320.gc452695387.dirty
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH net-next v3 01/47] dt-bindings: phy: Add Lynx 10G phy binding
2022-07-21 16:05 ` Sean Anderson
@ 2022-07-21 18:29 ` Rob Herring
2022-07-21 23:35 ` Sean Anderson
0 siblings, 1 reply; 30+ messages in thread
From: Rob Herring @ 2022-07-21 18:29 UTC (permalink / raw)
To: Sean Anderson
Cc: David S . Miller, Jakub Kicinski, Madalin Bucur, netdev,
Paolo Abeni, Eric Dumazet, linux-arm-kernel, Russell King,
linux-kernel@vger.kernel.org, Kishon Vijay Abraham I,
Krzysztof Kozlowski, Vinod Koul, devicetree,
open list:GENERIC PHY FRAMEWORK
On Thu, Jul 21, 2022 at 10:06 AM Sean Anderson <sean.anderson@seco.com> wrote:
>
>
>
> On 7/20/22 6:17 PM, Rob Herring wrote:
> > On Fri, Jul 15, 2022 at 05:59:08PM -0400, Sean Anderson wrote:
> >> This adds a binding for the SerDes module found on QorIQ processors. The
> >> phy reference has two cells, one for the first lane and one for the
> >> last. This should allow for good support of multi-lane protocols when
> >> (if) they are added. There is no protocol option, because the driver is
> >> designed to be able to completely reconfigure lanes at runtime.
> >> Generally, the phy consumer can select the appropriate protocol using
> >> set_mode. For the most part there is only one protocol controller
> >> (consumer) per lane/protocol combination. The exception to this is the
> >> B4860 processor, which has some lanes which can be connected to
> >> multiple MACs. For that processor, I anticipate the easiest way to
> >> resolve this will be to add an additional cell with a "protocol
> >> controller instance" property.
> >>
> >> Each serdes has a unique set of supported protocols (and lanes). The
> >> support matrix is configured in the device tree. The format of each
> >> PCCR (protocol configuration register) is modeled. Although the general
> >> format is typically the same across different SoCs, the specific
> >> supported protocols (and the values necessary to select them) are
> >> particular to individual SerDes. A nested structure is used to reduce
> >> duplication of data.
> >>
> >> There are two PLLs, each of which can be used as the master clock for
> >> each lane. Each PLL has its own reference. For the moment they are
> >> required, because it simplifies the driver implementation. Absent
> >> reference clocks can be modeled by a fixed-clock with a rate of 0.
> >>
> >> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
> >> ---
> >>
> >> Changes in v3:
> >> - Manually expand yaml references
> >> - Add mode configuration to device tree
> >>
> >> Changes in v2:
> >> - Rename to fsl,lynx-10g.yaml
> >> - Refer to the device in the documentation, rather than the binding
> >> - Move compatible first
> >> - Document phy cells in the description
> >> - Allow a value of 1 for phy-cells. This allows for compatibility with
> >> the similar (but according to Ioana Ciornei different enough) lynx-28g
> >> binding.
> >> - Remove minItems
> >> - Use list for clock-names
> >> - Fix example binding having too many cells in regs
> >> - Add #clock-cells. This will allow using assigned-clocks* to configure
> >> the PLLs.
> >> - Document the structure of the compatible strings
> >>
> >> .../devicetree/bindings/phy/fsl,lynx-10g.yaml | 311 ++++++++++++++++++
> >> 1 file changed, 311 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
> >>
> >> diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
> >> new file mode 100644
> >> index 000000000000..a2c37225bb67
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
> >> @@ -0,0 +1,311 @@
> >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >> +%YAML 1.2
> >> +---
> >> +$id: http://devicetree.org/schemas/phy/fsl,lynx-10g.yaml#
> >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >> +
> >> +title: NXP Lynx 10G SerDes
> >> +
> >> +maintainers:
> >> + - Sean Anderson <sean.anderson@seco.com>
> >> +
> >> +description: |
> >> + These Lynx "SerDes" devices are found in NXP's QorIQ line of processors. The
> >> + SerDes provides up to eight lanes. Each lane may be configured individually,
> >> + or may be combined with adjacent lanes for a multi-lane protocol. The SerDes
> >> + supports a variety of protocols, including up to 10G Ethernet, PCIe, SATA, and
> >> + others. The specific protocols supported for each lane depend on the
> >> + particular SoC.
> >> +
> >> +definitions:
> >
> > $defs:
>
> That didn't work until recently :)
>
> I will change this for next revision.
>
> >> + fsl,cfg:
> >> + $ref: /schemas/types.yaml#/definitions/uint32
> >> + minimum: 1
> >> + description: |
> >> + The configuration value to program into the field.
> >
> > What field?
>
> Ah, looks like this lost some context when I moved it. I will expand on this.
>
> >> +
> >> + fsl,first-lane:
> >> + $ref: /schemas/types.yaml#/definitions/uint32
> >> + minimum: 0
> >> + maximum: 7
> >> + description: |
> >> + The first lane in the group configured by fsl,cfg. This lane will have
> >> + the FIRST_LANE bit set in GCR0. The reset direction will also be set
> >> + based on whether this property is less than or greater than
> >> + fsl,last-lane.
> >> +
> >> + fsl,last-lane:
> >> + $ref: /schemas/types.yaml#/definitions/uint32
> >> + minimum: 0
> >> + maximum: 7
> >> + description: |
> >> + The last lane configured by fsl,cfg. If this property is absent,
> >> + then it will default to the value of fsl,first-lane.
> >> +
> >> +properties:
> >> + compatible:
> >> + items:
> >> + - enum:
> >> + - fsl,ls1046a-serdes
> >> + - fsl,ls1088a-serdes
> >> + - const: fsl,lynx-10g
> >> +
> >> + "#clock-cells":
> >> + const: 1
> >> + description: |
> >> + The cell contains the index of the PLL, starting from 0. Note that when
> >> + assigning a rate to a PLL, the PLLs' rates are divided by 1000 to avoid
> >> + overflow. A rate of 5000000 corresponds to 5GHz.
> >> +
> >> + "#phy-cells":
> >> + minimum: 1
> >> + maximum: 2
> >> + description: |
> >> + The cells contain the following arguments:
> >> + - The first lane in the group. Lanes are numbered based on the register
> >> + offsets, not the I/O ports. This corresponds to the letter-based ("Lane
> >> + A") naming scheme, and not the number-based ("Lane 0") naming scheme. On
> >> + most SoCs, "Lane A" is "Lane 0", but not always.
> >> + - Last lane. For single-lane protocols, this should be the same as the
> >> + first lane.
> >
> > Perhaps a single cell with a lane mask would be simpler.
>
> Yes.
>
> >> + If no lanes in a SerDes can be grouped, then #phy-cells may be 1, and the
> >> + first cell will specify the only lane in the group.
> >
> > It is generally easier to have a fixed number of cells.
>
> This was remarked on last time. I allowed this for better compatibility with the lynx
> 28g serdes binding. Is that reasonable? I agree it would simplify the driver to just
> have one cell type.
>
> >> +
> >> + clocks:
> >> + maxItems: 2
> >> + description: |
> >> + Clock for each PLL reference clock input.
> >> +
> >> + clock-names:
> >> + minItems: 2
> >> + maxItems: 2
> >> + items:
> >> + enum:
> >> + - ref0
> >> + - ref1
> >> +
> >> + reg:
> >> + maxItems: 1
> >> +
> >> +patternProperties:
> >> + '^pccr-':
> >> + type: object
> >> +
> >> + description: |
> >> + One of the protocol configuration registers (PCCRs). These contains
> >> + several fields, each of which mux a particular protocol onto a particular
> >> + lane.
> >> +
> >> + properties:
> >> + fsl,pccr:
> >> + $ref: /schemas/types.yaml#/definitions/uint32
> >> + description: |
> >> + The index of the PCCR. This is the same as the register name suffix.
> >> + For example, a node for PCCRB would use a value of '0xb' for an
> >> + offset of 0x22C (0x200 + 4 * 0xb).
> >> +
> >> + patternProperties:
> >> + '^(q?sgmii|xfi|pcie|sata)-':
> >> + type: object
> >> +
> >> + description: |
> >> + A configuration field within a PCCR. Each field configures one
> >> + protocol controller. The value of the field determines the lanes the
> >> + controller is connected to, if any.
> >> +
> >> + properties:
> >> + fsl,index:
> >
> > indexes are generally a red flag in binding. What is the index, how does
> > it correspond to the h/w and why do you need it.
>
> As described in the description below, the "index" is the protocol controller suffix,
> corresponding to a particular field (or set of fields) in the protocol configuration
> registers.
>
> > If we do end up needing
> > it, 'reg' is generally how we address some component.
>
> I originally used reg, but I got warnings about inheriting #size-cells and
> #address-cells. These bindings are already quite verbose to write out (there
> are around 10-20 configurations per SerDes to describe) and I would like to
> minimize the amount of properties to what is necessary. Additionally, this
> really describes a particular index of a field, and not a register (or an offset
> within a register).
Are you trying to describe all possible configurations in DT? Don't.
The DT should be the config for the specific board, not a menu of
possible configurations.
> >> + $ref: /schemas/types.yaml#/definitions/uint32
> >> + description: |
> >> + The index of the field. This corresponds to the suffix in the
> >
> > What field?
>
> The one from the description above.
>
> >> + documentation. For example, PEXa would be 0, PEXb 1, etc.
> >> + Generally, higher fields occupy lower bits.
> >> +
> >> + If there are any subnodes present, they will be preferred over
> >> + fsl,cfg et. al.
> >> +
> >> + fsl,cfg:
> >> + $ref: "#/definitions/fsl,cfg"
> >> +
> >> + fsl,first-lane:
> >> + $ref: "#/definitions/fsl,first-lane"
> >> +
> >> + fsl,last-lane:
> >> + $ref: "#/definitions/fsl,last-lane"
> >
> > Why do you have lane assignments here and in the phy cells?
>
> For three reasons. First, because we need to know what protocols are valid on what
> lanes. The idea is to allow the MAC to configure the protocols at runtime. To do
> this, someone has to figure out if the protocol is supported on that lane. The
> best place to put this IMO is the serdes.
Within ethernet protocols, that makes sense.
> Second, some serdes have (mostly) unsupported protocols such as PCIe as well as
> Ethernet protocols. To allow using Ethernet, we need to know which lanes are
> configured (by the firmware/bootloader) for some other protocol. That way, we
> can avoid touching them.
The ones needed for ethernet are the ones with a connection to the
ethernet MACs with the 'phys' properties. Why don't you just ignore
the !ethernet ones?
> Third, as part of the probe sequence, we need to ensure that no protocol controllers
> are currently selected. Otherwise, we will get strange problems later when we try
> to connect multiple protocol controllers to the same lane.
Sounds like a kernel problem...
>
> >> +
> >> + fsl,proto:
> >> + $ref: /schemas/types.yaml#/definitions/string
> >> + enum:
> >> + - sgmii
> >> + - sgmii25
> >> + - qsgmii
> >> + - xfi
> >> + - pcie
> >> + - sata
> >
> > We have standard phy modes already for at least most of these types.
> > Generally the mode is set in the phy cells.
>
> Yes, but this is the "protocol" which may correspond to multiple phy modes.
> For example, sgmii25 allows SGMII, 1000BASE-X, 1000BASE-KR, and 2500BASE-X
> phy modes.
As phy mode is more specific than protocol (or mode implies protocol),
why do we need protocol in DT?
[...]
> >> + xfi-1 {
> >> + fsl,index = <1>;
> >> + fsl,cfg = <0x1>;
> >> + fsl,first-lane = <0>;
> >> + fsl,proto = "xfi";
> >> + };
> >> + };
> >> + };
> >
> > Other than lane assignments and modes, I don't really understand what
> > you are trying to do.
>
> This is touched on a bit above, but the idea here is to allow for dynamic
> reconfiguration of the serdes mode in order to support multiple ethernet
> phy modes at runtime. To do this, we need to know about all the available
> protocol controllers, and the lanes they support. In particular, the
> available controllers and the lanes they map to (and the values to
> program to select them) differ even between different serdes on the same
> SoC.
>
> > It all looks too complex and I don't see any other
> > phy bindings needing something this complex.
>
> This was explicitly asked for last time. I also would not like to do this,
> but you and Krzysztof Kozlowski were very opposed to having per-device
> compatible strings. If you have a suggestion for a different approach, I
> am all ears. I find it very frustrating that the primary feedback I get from
> the device tree folks is "you can't do this" without a corresponding "do it
> this way."
How much time do you expect that we spend on your binding which is
only 1 out of the 100-200 patches we get a week? We're not experts in
all kinds of h/w and the experts for specific h/w don't always care
about DT bindings. We often get presented with solutions without
sufficient explanations of the problem. If I don't understand the
problem, how can I propose a solution? We can only point out what
doesn't fit within normal DT patterns. PHYs with multiple modes
supported is not a unique problem, so why are existing ways to deal
with that not sufficient and why do you need a *very* specific
binding?
With the phy binding, you know what each lane is connected to. You can
put whatever information you want in the phy cells to configure the
phy for that client. The phy cells are defined by the provider and
opaque to the consumer. Yes, we like to standardize cells when
possible, but that's only a convenience. I'm not saying phy cells is
the answer for everything and define 10 cells worth of data either.
Rob
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH net-next v3 01/47] dt-bindings: phy: Add Lynx 10G phy binding
2022-07-21 18:29 ` Rob Herring
@ 2022-07-21 23:35 ` Sean Anderson
2022-07-26 15:44 ` Sean Anderson
0 siblings, 1 reply; 30+ messages in thread
From: Sean Anderson @ 2022-07-21 23:35 UTC (permalink / raw)
To: Rob Herring
Cc: David S . Miller, Jakub Kicinski, Madalin Bucur, netdev,
Paolo Abeni, Eric Dumazet, linux-arm-kernel, Russell King,
linux-kernel@vger.kernel.org, Kishon Vijay Abraham I,
Krzysztof Kozlowski, Vinod Koul, devicetree,
open list:GENERIC PHY FRAMEWORK
On 7/21/22 2:29 PM, Rob Herring wrote:
> On Thu, Jul 21, 2022 at 10:06 AM Sean Anderson <sean.anderson@seco.com> wrote:
>>
>>
>>
>> On 7/20/22 6:17 PM, Rob Herring wrote:
>> > On Fri, Jul 15, 2022 at 05:59:08PM -0400, Sean Anderson wrote:
>> >> This adds a binding for the SerDes module found on QorIQ processors. The
>> >> phy reference has two cells, one for the first lane and one for the
>> >> last. This should allow for good support of multi-lane protocols when
>> >> (if) they are added. There is no protocol option, because the driver is
>> >> designed to be able to completely reconfigure lanes at runtime.
>> >> Generally, the phy consumer can select the appropriate protocol using
>> >> set_mode. For the most part there is only one protocol controller
>> >> (consumer) per lane/protocol combination. The exception to this is the
>> >> B4860 processor, which has some lanes which can be connected to
>> >> multiple MACs. For that processor, I anticipate the easiest way to
>> >> resolve this will be to add an additional cell with a "protocol
>> >> controller instance" property.
>> >>
>> >> Each serdes has a unique set of supported protocols (and lanes). The
>> >> support matrix is configured in the device tree. The format of each
>> >> PCCR (protocol configuration register) is modeled. Although the general
>> >> format is typically the same across different SoCs, the specific
>> >> supported protocols (and the values necessary to select them) are
>> >> particular to individual SerDes. A nested structure is used to reduce
>> >> duplication of data.
>> >>
>> >> There are two PLLs, each of which can be used as the master clock for
>> >> each lane. Each PLL has its own reference. For the moment they are
>> >> required, because it simplifies the driver implementation. Absent
>> >> reference clocks can be modeled by a fixed-clock with a rate of 0.
>> >>
>> >> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
>> >> ---
>> >>
>> >> Changes in v3:
>> >> - Manually expand yaml references
>> >> - Add mode configuration to device tree
>> >>
>> >> Changes in v2:
>> >> - Rename to fsl,lynx-10g.yaml
>> >> - Refer to the device in the documentation, rather than the binding
>> >> - Move compatible first
>> >> - Document phy cells in the description
>> >> - Allow a value of 1 for phy-cells. This allows for compatibility with
>> >> the similar (but according to Ioana Ciornei different enough) lynx-28g
>> >> binding.
>> >> - Remove minItems
>> >> - Use list for clock-names
>> >> - Fix example binding having too many cells in regs
>> >> - Add #clock-cells. This will allow using assigned-clocks* to configure
>> >> the PLLs.
>> >> - Document the structure of the compatible strings
>> >>
>> >> .../devicetree/bindings/phy/fsl,lynx-10g.yaml | 311 ++++++++++++++++++
>> >> 1 file changed, 311 insertions(+)
>> >> create mode 100644 Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
>> >>
>> >> diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
>> >> new file mode 100644
>> >> index 000000000000..a2c37225bb67
>> >> --- /dev/null
>> >> +++ b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
>> >> @@ -0,0 +1,311 @@
>> >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> >> +%YAML 1.2
>> >> +---
>> >> +$id: http://devicetree.org/schemas/phy/fsl,lynx-10g.yaml#
>> >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> >> +
>> >> +title: NXP Lynx 10G SerDes
>> >> +
>> >> +maintainers:
>> >> + - Sean Anderson <sean.anderson@seco.com>
>> >> +
>> >> +description: |
>> >> + These Lynx "SerDes" devices are found in NXP's QorIQ line of processors. The
>> >> + SerDes provides up to eight lanes. Each lane may be configured individually,
>> >> + or may be combined with adjacent lanes for a multi-lane protocol. The SerDes
>> >> + supports a variety of protocols, including up to 10G Ethernet, PCIe, SATA, and
>> >> + others. The specific protocols supported for each lane depend on the
>> >> + particular SoC.
>> >> +
>> >> +definitions:
>> >
>> > $defs:
>>
>> That didn't work until recently :)
>>
>> I will change this for next revision.
>>
>> >> + fsl,cfg:
>> >> + $ref: /schemas/types.yaml#/definitions/uint32
>> >> + minimum: 1
>> >> + description: |
>> >> + The configuration value to program into the field.
>> >
>> > What field?
>>
>> Ah, looks like this lost some context when I moved it. I will expand on this.
>>
>> >> +
>> >> + fsl,first-lane:
>> >> + $ref: /schemas/types.yaml#/definitions/uint32
>> >> + minimum: 0
>> >> + maximum: 7
>> >> + description: |
>> >> + The first lane in the group configured by fsl,cfg. This lane will have
>> >> + the FIRST_LANE bit set in GCR0. The reset direction will also be set
>> >> + based on whether this property is less than or greater than
>> >> + fsl,last-lane.
>> >> +
>> >> + fsl,last-lane:
>> >> + $ref: /schemas/types.yaml#/definitions/uint32
>> >> + minimum: 0
>> >> + maximum: 7
>> >> + description: |
>> >> + The last lane configured by fsl,cfg. If this property is absent,
>> >> + then it will default to the value of fsl,first-lane.
>> >> +
>> >> +properties:
>> >> + compatible:
>> >> + items:
>> >> + - enum:
>> >> + - fsl,ls1046a-serdes
>> >> + - fsl,ls1088a-serdes
>> >> + - const: fsl,lynx-10g
>> >> +
>> >> + "#clock-cells":
>> >> + const: 1
>> >> + description: |
>> >> + The cell contains the index of the PLL, starting from 0. Note that when
>> >> + assigning a rate to a PLL, the PLLs' rates are divided by 1000 to avoid
>> >> + overflow. A rate of 5000000 corresponds to 5GHz.
>> >> +
>> >> + "#phy-cells":
>> >> + minimum: 1
>> >> + maximum: 2
>> >> + description: |
>> >> + The cells contain the following arguments:
>> >> + - The first lane in the group. Lanes are numbered based on the register
>> >> + offsets, not the I/O ports. This corresponds to the letter-based ("Lane
>> >> + A") naming scheme, and not the number-based ("Lane 0") naming scheme. On
>> >> + most SoCs, "Lane A" is "Lane 0", but not always.
>> >> + - Last lane. For single-lane protocols, this should be the same as the
>> >> + first lane.
>> >
>> > Perhaps a single cell with a lane mask would be simpler.
>>
>> Yes.
>>
>> >> + If no lanes in a SerDes can be grouped, then #phy-cells may be 1, and the
>> >> + first cell will specify the only lane in the group.
>> >
>> > It is generally easier to have a fixed number of cells.
>>
>> This was remarked on last time. I allowed this for better compatibility with the lynx
>> 28g serdes binding. Is that reasonable? I agree it would simplify the driver to just
>> have one cell type.
>>
>> >> +
>> >> + clocks:
>> >> + maxItems: 2
>> >> + description: |
>> >> + Clock for each PLL reference clock input.
>> >> +
>> >> + clock-names:
>> >> + minItems: 2
>> >> + maxItems: 2
>> >> + items:
>> >> + enum:
>> >> + - ref0
>> >> + - ref1
>> >> +
>> >> + reg:
>> >> + maxItems: 1
>> >> +
>> >> +patternProperties:
>> >> + '^pccr-':
>> >> + type: object
>> >> +
>> >> + description: |
>> >> + One of the protocol configuration registers (PCCRs). These contains
>> >> + several fields, each of which mux a particular protocol onto a particular
>> >> + lane.
>> >> +
>> >> + properties:
>> >> + fsl,pccr:
>> >> + $ref: /schemas/types.yaml#/definitions/uint32
>> >> + description: |
>> >> + The index of the PCCR. This is the same as the register name suffix.
>> >> + For example, a node for PCCRB would use a value of '0xb' for an
>> >> + offset of 0x22C (0x200 + 4 * 0xb).
>> >> +
>> >> + patternProperties:
>> >> + '^(q?sgmii|xfi|pcie|sata)-':
>> >> + type: object
>> >> +
>> >> + description: |
>> >> + A configuration field within a PCCR. Each field configures one
>> >> + protocol controller. The value of the field determines the lanes the
>> >> + controller is connected to, if any.
>> >> +
>> >> + properties:
>> >> + fsl,index:
>> >
>> > indexes are generally a red flag in binding. What is the index, how does
>> > it correspond to the h/w and why do you need it.
>>
>> As described in the description below, the "index" is the protocol controller suffix,
>> corresponding to a particular field (or set of fields) in the protocol configuration
>> registers.
>>
>> > If we do end up needing
>> > it, 'reg' is generally how we address some component.
>>
>> I originally used reg, but I got warnings about inheriting #size-cells and
>> #address-cells. These bindings are already quite verbose to write out (there
>> are around 10-20 configurations per SerDes to describe) and I would like to
>> minimize the amount of properties to what is necessary. Additionally, this
>> really describes a particular index of a field, and not a register (or an offset
>> within a register).
>
> Are you trying to describe all possible configurations in DT? Don't.
> The DT should be the config for the specific board, not a menu of
> possible configurations.
Reasons 2 and 3 mentioned below.
>> >> + $ref: /schemas/types.yaml#/definitions/uint32
>> >> + description: |
>> >> + The index of the field. This corresponds to the suffix in the
>> >
>> > What field?
>>
>> The one from the description above.
>>
>> >> + documentation. For example, PEXa would be 0, PEXb 1, etc.
>> >> + Generally, higher fields occupy lower bits.
>> >> +
>> >> + If there are any subnodes present, they will be preferred over
>> >> + fsl,cfg et. al.
>> >> +
>> >> + fsl,cfg:
>> >> + $ref: "#/definitions/fsl,cfg"
>> >> +
>> >> + fsl,first-lane:
>> >> + $ref: "#/definitions/fsl,first-lane"
>> >> +
>> >> + fsl,last-lane:
>> >> + $ref: "#/definitions/fsl,last-lane"
>> >
>> > Why do you have lane assignments here and in the phy cells?
>>
>> For three reasons. First, because we need to know what protocols are valid on what
>> lanes. The idea is to allow the MAC to configure the protocols at runtime. To do
>> this, someone has to figure out if the protocol is supported on that lane. The
>> best place to put this IMO is the serdes.
>
> Within ethernet protocols, that makes sense.
>
>> Second, some serdes have (mostly) unsupported protocols such as PCIe as well as
>> Ethernet protocols. To allow using Ethernet, we need to know which lanes are
>> configured (by the firmware/bootloader) for some other protocol. That way, we
>> can avoid touching them.
>
> The ones needed for ethernet are the ones with a connection to the
> ethernet MACs with the 'phys' properties. Why don't you just ignore
> the !ethernet ones?
That's what I try to do. However, non-ethernet modes can use the same
lanes as ethernet modes. So we need to know how the protocol selection
registers are laid out, and what bits select which lanes. Although the
general layout is mostly the same [1], the mapping is specific to the
individual serdes on the individual SoC.
[1] Occasionally, the layout of registers changes between different SoC
revisions. Usually this is because one of the registers ran out of
bits.
>> Third, as part of the probe sequence, we need to ensure that no protocol controllers
>> are currently selected. Otherwise, we will get strange problems later when we try
>> to connect multiple protocol controllers to the same lane.
>
> Sounds like a kernel problem...
Of course, but this stuff has to come from somewhere. Due to the second
reason above we can't just clear out all the PCCRs. We need to know
whether a lane is in use or not,
>>
>> >> +
>> >> + fsl,proto:
>> >> + $ref: /schemas/types.yaml#/definitions/string
>> >> + enum:
>> >> + - sgmii
>> >> + - sgmii25
>> >> + - qsgmii
>> >> + - xfi
>> >> + - pcie
>> >> + - sata
>> >
>> > We have standard phy modes already for at least most of these types.
>> > Generally the mode is set in the phy cells.
>>
>> Yes, but this is the "protocol" which may correspond to multiple phy modes.
>> For example, sgmii25 allows SGMII, 1000BASE-X, 1000BASE-KR, and 2500BASE-X
>> phy modes.
>
> As phy mode is more specific than protocol (or mode implies protocol),
> why do we need protocol in DT?
The protocol (along with the PCCR and the protocol controller index) is
used to determine the bitmask for a particular selector. For example,
PCCR1 on the T1040 has the following layout:
Bits Field name
===== ==========
0- 1 SGMIIA_CFG
2- 3 SGMIIB_CFG
4- 5 SGMIIC_CFG
6- 7 SGMIID_CFG
8- 9 SGMIIE_CFG
10-11 SGMIIF_CFG
12-15 Reserved
16 SGMIIA_KX
17 SGMIIB_KX
18 SGMIIC_KX
19 SGMIID_KX
20 SGMIIE_KX
21 SGMIIF_KX
22-23 Reserved
24-25 QSGMA_CFG
26-27 Reserved
28-29 QSGMB_CFG
30-31 Reserved
Note that the KX bit (determining whether 1000BASE-X/SGMII or
1000BASE-KX is enabled) is not contiguous with the CFG field. Instead,
the "index" of the protocol controller is used to determine the correct
max to use for the CFG field as well as the KX bit. Also note that this
register is inhomogeneous. Just the "index" is not enough: we need to
know what the protocol is as well.
> [...]
>
>> >> + xfi-1 {
>> >> + fsl,index = <1>;
>> >> + fsl,cfg = <0x1>;
>> >> + fsl,first-lane = <0>;
>> >> + fsl,proto = "xfi";
>> >> + };
>> >> + };
>> >> + };
>> >
>> > Other than lane assignments and modes, I don't really understand what
>> > you are trying to do.
>>
>> This is touched on a bit above, but the idea here is to allow for dynamic
>> reconfiguration of the serdes mode in order to support multiple ethernet
>> phy modes at runtime. To do this, we need to know about all the available
>> protocol controllers, and the lanes they support. In particular, the
>> available controllers and the lanes they map to (and the values to
>> program to select them) differ even between different serdes on the same
>> SoC.
>>
>> > It all looks too complex and I don't see any other
>> > phy bindings needing something this complex.
>>
>> This was explicitly asked for last time. I also would not like to do this,
>> but you and Krzysztof Kozlowski were very opposed to having per-device
>> compatible strings. If you have a suggestion for a different approach, I
>> am all ears. I find it very frustrating that the primary feedback I get from
>> the device tree folks is "you can't do this" without a corresponding "do it
>> this way."
>
> How much time do you expect that we spend on your binding which is
> only 1 out of the 100-200 patches we get a week?
I appreciate the work you do on this. But every revision I make without
knowing whether I'm on the right track wastes both of our time. I have
to spend my time coming up with and implementing a new binding and you
have to spend time reviewing it. A nudge in the right direction can
easily save us both time.
> We're not experts in all kinds of h/w and the experts for specific h/w
> don't always care about DT bindings.
Vinod, this is why I (and presumably Rob) would appreciate your feedback.
> We often get presented with solutions without sufficient explanations
> of the problem. If I don't understand the problem, how can I propose a
> solution? We can only point out what doesn't fit within normal DT
> patterns. PHYs with multiple modes supported is not a unique problem,
> so why are existing ways to deal with that not sufficient and why do
> you need a *very* specific binding?
Well, take for example xlnx,zynqmp-psgtr. Although it is not obvious
from the binding, there are several things which simplify the driver.
First, all the modes are completely incompatible. Any consumer will not
need to switch modes at runtime. Second, there is only one GTR device
per SoC. That means that the compatible string which completely
determines the available modes. The mode/lane mapping can be stored in
the driver instead of in the device tree. Last, there is only one
variant of this device. There are no other SoCs with slightly different
register layout, mode support, or lanes.
To contrast with this device, there are several almost-compatible modes.
We cannot just set the mode at boot and be done with it (in fact this is
exactly what I am trying to change by adding a driver). Some modes are
so similar that they reuse protocol controllers, but they still need to
have different lane configuration. There are multiple different SerDes
devices on each SoC. While they have the same register layout, the
connected protocol controllers (and lane mapping) is different. There
are also different SoCs with (ever-so-slightly) different register
layouts, protocol controllers, and lane mappings.
All of this sort of information would normally just be stored in the
driver as a set of struct arrays. In fact, this is what I did the first
time!
> With the phy binding, you know what each lane is connected to. You can
> put whatever information you want in the phy cells to configure the
> phy for that client. The phy cells are defined by the provider and
> opaque to the consumer. Yes, we like to standardize cells when
> possible, but that's only a convenience. I'm not saying phy cells is
> the answer for everything and define 10 cells worth of data either.
Maybe it's better to do something like
// first-lane last-lane protocol pccr idx val
phys = <&serdes1 1 1 PHY_TYPE_SGMII 0x8 2 1>,
<&serdes1 1 1 PHY_TYPE_QSGMII 0x9 0 2>,
<&serdes1 1 1 PHY_TYPE_10GBASER 0xb 1 1>;
phy-names = "sgmii", "qsgmii", "xfi";
(made up values)
But this doesn't play well with the existing idiom of being able to call
phy_set_mode(). Plus, existing drivers expect to have one (devicetree)
phy for one physical serdes.
What about
phys = <&serdes1_lane1>;
and then under the serdes node do something like
serdes1: phy@foo {
...
serdes1_lane1 {
first-lane = <1>;
sgmii {
fsl,pccr = <0x8>;
fsl,idx = <2>;
fsl,cfg = <1>;
fsl,proto = "sgmii";
// or PHY_TYPE_SGMII
};
qsgmii {
...
};
xfi {
...
};
};
};
and this way you could have something like a fsl,reserved property to
deal with not-yet-supported lanes. And this could be added piecemeal by
board configs.
--Sean
^ permalink raw reply [flat|nested] 30+ messages in thread
* RE: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes bindings
2022-07-21 15:40 ` Sean Anderson
@ 2022-07-22 12:41 ` Camelia Alexandra Groza
2022-07-25 20:02 ` Sean Anderson
0 siblings, 1 reply; 30+ messages in thread
From: Camelia Alexandra Groza @ 2022-07-22 12:41 UTC (permalink / raw)
To: Sean Anderson, David S . Miller, Jakub Kicinski, Madalin Bucur,
netdev@vger.kernel.org
Cc: Paolo Abeni, Eric Dumazet, linux-arm-kernel@lists.infradead.org,
Russell King, linux-kernel@vger.kernel.org,
Kishon Vijay Abraham I, Krzysztof Kozlowski, Leo Li, Rob Herring,
Shawn Guo, Vinod Koul, devicetree@vger.kernel.org,
linux-phy@lists.infradead.org
> -----Original Message-----
> From: Sean Anderson <sean.anderson@seco.com>
> Sent: Thursday, July 21, 2022 18:41
> To: Camelia Alexandra Groza <camelia.groza@nxp.com>; David S . Miller
> <davem@davemloft.net>; Jakub Kicinski <kuba@kernel.org>; Madalin Bucur
> <madalin.bucur@nxp.com>; netdev@vger.kernel.org
> Cc: Paolo Abeni <pabeni@redhat.com>; Eric Dumazet
> <edumazet@google.com>; linux-arm-kernel@lists.infradead.org; Russell
> King <linux@armlinux.org.uk>; linux-kernel@vger.kernel.org; Kishon Vijay
> Abraham I <kishon@ti.com>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@linaro.org>; Leo Li <leoyang.li@nxp.com>; Rob
> Herring <robh+dt@kernel.org>; Shawn Guo <shawnguo@kernel.org>; Vinod
> Koul <vkoul@kernel.org>; devicetree@vger.kernel.org; linux-
> phy@lists.infradead.org
> Subject: Re: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes
> bindings
>
>
>
> On 7/21/22 10:20 AM, Camelia Alexandra Groza wrote:
> >> -----Original Message-----
> >> From: Sean Anderson <sean.anderson@seco.com>
> >> Sent: Saturday, July 16, 2022 1:00
> >> To: David S . Miller <davem@davemloft.net>; Jakub Kicinski
> >> <kuba@kernel.org>; Madalin Bucur <madalin.bucur@nxp.com>;
> >> netdev@vger.kernel.org
> >> Cc: Paolo Abeni <pabeni@redhat.com>; Eric Dumazet
> >> <edumazet@google.com>; linux-arm-kernel@lists.infradead.org; Russell
> >> King <linux@armlinux.org.uk>; linux-kernel@vger.kernel.org; Sean
> Anderson
> >> <sean.anderson@seco.com>; Kishon Vijay Abraham I <kishon@ti.com>;
> >> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Leo Li
> >> <leoyang.li@nxp.com>; Rob Herring <robh+dt@kernel.org>; Shawn Guo
> >> <shawnguo@kernel.org>; Vinod Koul <vkoul@kernel.org>;
> >> devicetree@vger.kernel.org; linux-phy@lists.infradead.org
> >> Subject: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes
> >> bindings
> >>
> >> This adds appropriate bindings for the macs which use the SerDes. The
> >> 156.25MHz fixed clock is a crystal. The 100MHz clocks (there are
> >> actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is
> >> no driver for this device (and as far as I know all you can do with the
> >> 100MHz clocks is gate them), so I have chosen to model it as a single
> >> fixed clock.
> >>
> >> Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
> >> This means that Lane A (what the driver thinks is lane 0) uses pins
> >> SD1_TX3_P/N.
> >>
> >> Because this will break ethernet if the serdes is not enabled, enable
> >> the serdes driver by default on Layerscape.
> >>
> >> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
> >> ---
> >> Please let me know if there is a better/more specific config I can use
> >> here.
> >>
> >> (no changes since v1)
> >
> > My LS1046ARDB hangs at boot with this patch right after the second SerDes
> is probed,
> > right before the point where the PCI host bridge is registered. I can get
> around this
> > either by disabling the second SerDes node from the device tree, or
> disabling
> > CONFIG_PCI_LAYERSCAPE at build.
> >
> > I haven't debugged it more but there seems to be an issue here.
>
> Hm. Do you have anything plugged into the PCIe/SATA slots? I haven't been
> testing with
> anything there. For now, it may be better to just leave it disabled.
>
> --Sean
Yes, I have an Intel e1000 card plugged in.
Camelia
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH net-next v3 03/47] dt-bindings: net: Convert FMan MAC bindings to yaml
2022-07-21 14:42 ` Krzysztof Kozlowski
@ 2022-07-22 16:50 ` Sean Anderson
0 siblings, 0 replies; 30+ messages in thread
From: Sean Anderson @ 2022-07-22 16:50 UTC (permalink / raw)
To: Krzysztof Kozlowski, Rob Herring
Cc: devicetree, Rob Herring, Russell King, netdev, Paolo Abeni,
Madalin Bucur, Eric Dumazet, David S . Miller,
Krzysztof Kozlowski, Jakub Kicinski, linux-arm-kernel,
linux-kernel
On 7/21/22 10:42 AM, Krzysztof Kozlowski wrote:
> On 17/07/2022 00:47, Sean Anderson wrote:
>> On 7/15/22 7:06 PM, Rob Herring wrote:
>>> On Fri, 15 Jul 2022 17:59:10 -0400, Sean Anderson wrote:
>>>> This converts the MAC portion of the FMan MAC bindings to yaml.
>>>>
>>>> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
>>>> Reviewed-by: Rob Herring <robh@kernel.org>
>>>> ---
>>>>
>>>> Changes in v3:
>>>> - Incorporate some minor changes into the first FMan binding commit
>>>>
>>>> Changes in v2:
>>>> - New
>>>>
>>>> .../bindings/net/fsl,fman-dtsec.yaml | 145 ++++++++++++++++++
>>>> .../devicetree/bindings/net/fsl-fman.txt | 128 +---------------
>>>> 2 files changed, 146 insertions(+), 127 deletions(-)
>>>> create mode 100644 Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
>>>>
>>>
>>> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
>>> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>>>
>>> yamllint warnings/errors:
>>>
>>> dtschema/dtc warnings/errors:
>>> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/fsl,fman-dtsec.example.dtb: ethernet@e8000: 'phy-connection-type', 'phy-handle' do not match any of the regexes: 'pinctrl-[0-9]+'
>>> From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
>>>
>>> doc reference errors (make refcheckdocs):
>>
>> What's the correct way to do this? I have '$ref: ethernet-controller.yaml#'
>> under allOf, but it doesn't seem to apply. IIRC this doesn't occur for actual dts files.
>
> You do not allow any other properties than explicitly listed
> (additionalProp:false). If you want to apply all properties from other
> schema you need to use unevaluated.
>
> https://elixir.bootlin.com/linux/v5.19-rc7/source/Documentation/devicetree/bindings/writing-bindings.rst#L75
Thanks, I'll fix that.
Although I wasn't able to reproduce this error locally. I'm using the
following command:
CROSS_COMPILE=aarch64-linux-gnu- ARCH=arm64 make O=build -j12 dt_binding_check DT_SCHEMA_FILES=fsl,fman-dtsec.yaml DT_CHECKER_FLAGS=-m
--Sean
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes bindings
2022-07-22 12:41 ` Camelia Alexandra Groza
@ 2022-07-25 20:02 ` Sean Anderson
2022-07-26 11:35 ` Camelia Alexandra Groza
0 siblings, 1 reply; 30+ messages in thread
From: Sean Anderson @ 2022-07-25 20:02 UTC (permalink / raw)
To: Camelia Alexandra Groza, David S . Miller, Jakub Kicinski,
Madalin Bucur, netdev@vger.kernel.org
Cc: Paolo Abeni, Eric Dumazet, linux-arm-kernel@lists.infradead.org,
Russell King, linux-kernel@vger.kernel.org,
Kishon Vijay Abraham I, Krzysztof Kozlowski, Leo Li, Rob Herring,
Shawn Guo, Vinod Koul, devicetree@vger.kernel.org,
linux-phy@lists.infradead.org
On 7/22/22 8:41 AM, Camelia Alexandra Groza wrote:
>> -----Original Message-----
>> From: Sean Anderson <sean.anderson@seco.com>
>> Sent: Thursday, July 21, 2022 18:41
>> To: Camelia Alexandra Groza <camelia.groza@nxp.com>; David S . Miller
>> <davem@davemloft.net>; Jakub Kicinski <kuba@kernel.org>; Madalin Bucur
>> <madalin.bucur@nxp.com>; netdev@vger.kernel.org
>> Cc: Paolo Abeni <pabeni@redhat.com>; Eric Dumazet
>> <edumazet@google.com>; linux-arm-kernel@lists.infradead.org; Russell
>> King <linux@armlinux.org.uk>; linux-kernel@vger.kernel.org; Kishon Vijay
>> Abraham I <kishon@ti.com>; Krzysztof Kozlowski
>> <krzysztof.kozlowski+dt@linaro.org>; Leo Li <leoyang.li@nxp.com>; Rob
>> Herring <robh+dt@kernel.org>; Shawn Guo <shawnguo@kernel.org>; Vinod
>> Koul <vkoul@kernel.org>; devicetree@vger.kernel.org; linux-
>> phy@lists.infradead.org
>> Subject: Re: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes
>> bindings
>>
>>
>>
>> On 7/21/22 10:20 AM, Camelia Alexandra Groza wrote:
>> >> -----Original Message-----
>> >> From: Sean Anderson <sean.anderson@seco.com>
>> >> Sent: Saturday, July 16, 2022 1:00
>> >> To: David S . Miller <davem@davemloft.net>; Jakub Kicinski
>> >> <kuba@kernel.org>; Madalin Bucur <madalin.bucur@nxp.com>;
>> >> netdev@vger.kernel.org
>> >> Cc: Paolo Abeni <pabeni@redhat.com>; Eric Dumazet
>> >> <edumazet@google.com>; linux-arm-kernel@lists.infradead.org; Russell
>> >> King <linux@armlinux.org.uk>; linux-kernel@vger.kernel.org; Sean
>> Anderson
>> >> <sean.anderson@seco.com>; Kishon Vijay Abraham I <kishon@ti.com>;
>> >> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Leo Li
>> >> <leoyang.li@nxp.com>; Rob Herring <robh+dt@kernel.org>; Shawn Guo
>> >> <shawnguo@kernel.org>; Vinod Koul <vkoul@kernel.org>;
>> >> devicetree@vger.kernel.org; linux-phy@lists.infradead.org
>> >> Subject: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes
>> >> bindings
>> >>
>> >> This adds appropriate bindings for the macs which use the SerDes. The
>> >> 156.25MHz fixed clock is a crystal. The 100MHz clocks (there are
>> >> actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is
>> >> no driver for this device (and as far as I know all you can do with the
>> >> 100MHz clocks is gate them), so I have chosen to model it as a single
>> >> fixed clock.
>> >>
>> >> Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
>> >> This means that Lane A (what the driver thinks is lane 0) uses pins
>> >> SD1_TX3_P/N.
>> >>
>> >> Because this will break ethernet if the serdes is not enabled, enable
>> >> the serdes driver by default on Layerscape.
>> >>
>> >> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
>> >> ---
>> >> Please let me know if there is a better/more specific config I can use
>> >> here.
>> >>
>> >> (no changes since v1)
>> >
>> > My LS1046ARDB hangs at boot with this patch right after the second SerDes
>> is probed,
>> > right before the point where the PCI host bridge is registered. I can get
>> around this
>> > either by disabling the second SerDes node from the device tree, or
>> disabling
>> > CONFIG_PCI_LAYERSCAPE at build.
>> >
>> > I haven't debugged it more but there seems to be an issue here.
>>
>> Hm. Do you have anything plugged into the PCIe/SATA slots? I haven't been
>> testing with
>> anything there. For now, it may be better to just leave it disabled.
>>
>> --Sean
>
> Yes, I have an Intel e1000 card plugged in.
>
> Camelia
>
Can you try the following patch? I was able to boot with PCI with it applied.
From 71f4136f1bdda89009936a9c24561b60e0554859 Mon Sep 17 00:00:00 2001
From: Sean Anderson <sean.anderson@seco.com>
Date: Mon, 25 Jul 2022 16:01:16 -0400
Subject: [PATCH] arm64: dts: ls1046a: Fix missing PCIe lane
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 0b3765cad383..3841ba274782 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -532,7 +532,7 @@ pcie-0 {
/* PCIe.1 x1 */
cfg-1 {
fsl,cfg = <0x1>;
- fsl,first-lane = <1>;
+ fsl,first-lane = <0>;
};
/* PCIe.1 x4 */
@@ -543,6 +543,14 @@ cfg-3 {
};
};
+ /* PCIe.2 x1 */
+ pcie-1 {
+ fsl,index = <1>;
+ fsl,proto = "pcie";
+ fsl,cfg = <0x1>;
+ fsl,first-lane = <1>;
+ };
+
pcie-2 {
fsl,index = <2>;
fsl,proto = "pcie";
--
2.35.1.1320.gc452695387.dirty
^ permalink raw reply related [flat|nested] 30+ messages in thread
* RE: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes bindings
2022-07-25 20:02 ` Sean Anderson
@ 2022-07-26 11:35 ` Camelia Alexandra Groza
0 siblings, 0 replies; 30+ messages in thread
From: Camelia Alexandra Groza @ 2022-07-26 11:35 UTC (permalink / raw)
To: Sean Anderson, David S . Miller, Jakub Kicinski, Madalin Bucur,
netdev@vger.kernel.org
Cc: Paolo Abeni, Eric Dumazet, linux-arm-kernel@lists.infradead.org,
Russell King, linux-kernel@vger.kernel.org,
Kishon Vijay Abraham I, Krzysztof Kozlowski, Leo Li, Rob Herring,
Shawn Guo, Vinod Koul, devicetree@vger.kernel.org,
linux-phy@lists.infradead.org
> -----Original Message-----
> From: Sean Anderson <sean.anderson@seco.com>
> Sent: Monday, July 25, 2022 23:02
> To: Camelia Alexandra Groza <camelia.groza@nxp.com>; David S . Miller
> <davem@davemloft.net>; Jakub Kicinski <kuba@kernel.org>; Madalin Bucur
> <madalin.bucur@nxp.com>; netdev@vger.kernel.org
> Cc: Paolo Abeni <pabeni@redhat.com>; Eric Dumazet
> <edumazet@google.com>; linux-arm-kernel@lists.infradead.org; Russell
> King <linux@armlinux.org.uk>; linux-kernel@vger.kernel.org; Kishon Vijay
> Abraham I <kishon@ti.com>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@linaro.org>; Leo Li <leoyang.li@nxp.com>; Rob
> Herring <robh+dt@kernel.org>; Shawn Guo <shawnguo@kernel.org>; Vinod
> Koul <vkoul@kernel.org>; devicetree@vger.kernel.org; linux-
> phy@lists.infradead.org
> Subject: Re: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes
> bindings
>
>
>
> On 7/22/22 8:41 AM, Camelia Alexandra Groza wrote:
> >> -----Original Message-----
> >> From: Sean Anderson <sean.anderson@seco.com>
> >> Sent: Thursday, July 21, 2022 18:41
> >> To: Camelia Alexandra Groza <camelia.groza@nxp.com>; David S . Miller
> >> <davem@davemloft.net>; Jakub Kicinski <kuba@kernel.org>; Madalin
> Bucur
> >> <madalin.bucur@nxp.com>; netdev@vger.kernel.org
> >> Cc: Paolo Abeni <pabeni@redhat.com>; Eric Dumazet
> >> <edumazet@google.com>; linux-arm-kernel@lists.infradead.org; Russell
> >> King <linux@armlinux.org.uk>; linux-kernel@vger.kernel.org; Kishon Vijay
> >> Abraham I <kishon@ti.com>; Krzysztof Kozlowski
> >> <krzysztof.kozlowski+dt@linaro.org>; Leo Li <leoyang.li@nxp.com>; Rob
> >> Herring <robh+dt@kernel.org>; Shawn Guo <shawnguo@kernel.org>;
> Vinod
> >> Koul <vkoul@kernel.org>; devicetree@vger.kernel.org; linux-
> >> phy@lists.infradead.org
> >> Subject: Re: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add
> serdes
> >> bindings
> >>
> >>
> >>
> >> On 7/21/22 10:20 AM, Camelia Alexandra Groza wrote:
> >> >> -----Original Message-----
> >> >> From: Sean Anderson <sean.anderson@seco.com>
> >> >> Sent: Saturday, July 16, 2022 1:00
> >> >> To: David S . Miller <davem@davemloft.net>; Jakub Kicinski
> >> >> <kuba@kernel.org>; Madalin Bucur <madalin.bucur@nxp.com>;
> >> >> netdev@vger.kernel.org
> >> >> Cc: Paolo Abeni <pabeni@redhat.com>; Eric Dumazet
> >> >> <edumazet@google.com>; linux-arm-kernel@lists.infradead.org;
> Russell
> >> >> King <linux@armlinux.org.uk>; linux-kernel@vger.kernel.org; Sean
> >> Anderson
> >> >> <sean.anderson@seco.com>; Kishon Vijay Abraham I
> <kishon@ti.com>;
> >> >> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Leo Li
> >> >> <leoyang.li@nxp.com>; Rob Herring <robh+dt@kernel.org>; Shawn
> Guo
> >> >> <shawnguo@kernel.org>; Vinod Koul <vkoul@kernel.org>;
> >> >> devicetree@vger.kernel.org; linux-phy@lists.infradead.org
> >> >> Subject: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes
> >> >> bindings
> >> >>
> >> >> This adds appropriate bindings for the macs which use the SerDes. The
> >> >> 156.25MHz fixed clock is a crystal. The 100MHz clocks (there are
> >> >> actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There
> is
> >> >> no driver for this device (and as far as I know all you can do with the
> >> >> 100MHz clocks is gate them), so I have chosen to model it as a single
> >> >> fixed clock.
> >> >>
> >> >> Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
> >> >> This means that Lane A (what the driver thinks is lane 0) uses pins
> >> >> SD1_TX3_P/N.
> >> >>
> >> >> Because this will break ethernet if the serdes is not enabled, enable
> >> >> the serdes driver by default on Layerscape.
> >> >>
> >> >> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
> >> >> ---
> >> >> Please let me know if there is a better/more specific config I can use
> >> >> here.
> >> >>
> >> >> (no changes since v1)
> >> >
> >> > My LS1046ARDB hangs at boot with this patch right after the second
> SerDes
> >> is probed,
> >> > right before the point where the PCI host bridge is registered. I can get
> >> around this
> >> > either by disabling the second SerDes node from the device tree, or
> >> disabling
> >> > CONFIG_PCI_LAYERSCAPE at build.
> >> >
> >> > I haven't debugged it more but there seems to be an issue here.
> >>
> >> Hm. Do you have anything plugged into the PCIe/SATA slots? I haven't
> been
> >> testing with
> >> anything there. For now, it may be better to just leave it disabled.
> >>
> >> --Sean
> >
> > Yes, I have an Intel e1000 card plugged in.
> >
> > Camelia
> >
>
> Can you try the following patch? I was able to boot with PCI with it applied.
Works for me as well. The board boots fine and the PCI card is functional. Thanks.
> From 71f4136f1bdda89009936a9c24561b60e0554859 Mon Sep 17 00:00:00
> 2001
> From: Sean Anderson <sean.anderson@seco.com>
> Date: Mon, 25 Jul 2022 16:01:16 -0400
> Subject: [PATCH] arm64: dts: ls1046a: Fix missing PCIe lane
>
> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> index 0b3765cad383..3841ba274782 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> @@ -532,7 +532,7 @@ pcie-0 {
> /* PCIe.1 x1 */
> cfg-1 {
> fsl,cfg = <0x1>;
> - fsl,first-lane = <1>;
> + fsl,first-lane = <0>;
> };
>
> /* PCIe.1 x4 */
> @@ -543,6 +543,14 @@ cfg-3 {
> };
> };
>
> + /* PCIe.2 x1 */
> + pcie-1 {
> + fsl,index = <1>;
> + fsl,proto = "pcie";
> + fsl,cfg = <0x1>;
> + fsl,first-lane = <1>;
> + };
> +
> pcie-2 {
> fsl,index = <2>;
> fsl,proto = "pcie";
> --
> 2.35.1.1320.gc452695387.dirty
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH net-next v3 01/47] dt-bindings: phy: Add Lynx 10G phy binding
2022-07-21 23:35 ` Sean Anderson
@ 2022-07-26 15:44 ` Sean Anderson
0 siblings, 0 replies; 30+ messages in thread
From: Sean Anderson @ 2022-07-26 15:44 UTC (permalink / raw)
To: Rob Herring
Cc: David S . Miller, Jakub Kicinski, Madalin Bucur, netdev,
Paolo Abeni, Eric Dumazet, linux-arm-kernel, Russell King,
linux-kernel@vger.kernel.org, Kishon Vijay Abraham I,
Krzysztof Kozlowski, Vinod Koul, devicetree,
open list:GENERIC PHY FRAMEWORK
Hi Rob,
On 7/21/22 7:35 PM, Sean Anderson wrote:
> What about
>
> phys = <&serdes1_lane1>;
>
> and then under the serdes node do something like
>
> serdes1: phy@foo {
> ...
>
> serdes1_lane1 {
> first-lane = <1>;
>
> sgmii {
> fsl,pccr = <0x8>;
> fsl,idx = <2>;
> fsl,cfg = <1>;
> fsl,proto = "sgmii";
> // or PHY_TYPE_SGMII
> };
>
> qsgmii {
> ...
> };
>
> xfi {
> ...
> };
> };
> };
>
> and this way you could have something like a fsl,reserved property to
> deal with not-yet-supported lanes. And this could be added piecemeal by
> board configs.
Does this sound good? I would like to start working on v4 of this series,
and reworking the binding will be a big part of that. Am I heading in the
right direction? This seems to be a more common approach (e.g. mediatek,tphy).
--Sean
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2022-07-26 15:45 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-07-15 21:59 [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink Sean Anderson
2022-07-15 21:59 ` [PATCH net-next v3 01/47] dt-bindings: phy: Add Lynx 10G phy binding Sean Anderson
2022-07-20 22:17 ` Rob Herring
2022-07-21 16:05 ` Sean Anderson
2022-07-21 18:29 ` Rob Herring
2022-07-21 23:35 ` Sean Anderson
2022-07-26 15:44 ` Sean Anderson
2022-07-15 21:59 ` [PATCH net-next v3 03/47] dt-bindings: net: Convert FMan MAC bindings to yaml Sean Anderson
2022-07-15 23:06 ` Rob Herring
2022-07-16 22:47 ` Sean Anderson
2022-07-21 14:42 ` Krzysztof Kozlowski
2022-07-22 16:50 ` Sean Anderson
2022-07-15 21:59 ` [PATCH net-next v3 04/47] dt-bindings: net: fman: Add additional interface properties Sean Anderson
2022-07-15 21:59 ` [PATCH net-next v3 06/47] [RFT] phy: fsl: Add Lynx 10G SerDes driver Sean Anderson
2022-07-16 22:39 ` kernel test robot
2022-07-15 21:59 ` [PATCH net-next v3 42/47] powerpc: dts: qoriq: Add nodes for QSGMII PCSs Sean Anderson
2022-07-21 13:48 ` Camelia Alexandra Groza
2022-07-21 17:51 ` Sean Anderson
2022-07-15 21:59 ` [PATCH net-next v3 43/47] arm64: dts: layerscape: " Sean Anderson
2022-07-15 21:59 ` [PATCH net-next v3 44/47] arm64: dts: ls1046a: Add serdes bindings Sean Anderson
2022-07-15 21:59 ` [PATCH net-next v3 45/47] arm64: dts: ls1088a: " Sean Anderson
2022-07-15 21:59 ` [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: " Sean Anderson
2022-07-21 14:20 ` Camelia Alexandra Groza
2022-07-21 15:40 ` Sean Anderson
2022-07-22 12:41 ` Camelia Alexandra Groza
2022-07-25 20:02 ` Sean Anderson
2022-07-26 11:35 ` Camelia Alexandra Groza
2022-07-15 21:59 ` [PATCH net-next v3 47/47] [WIP] arm64: dts: ls1088ardb: " Sean Anderson
2022-07-21 14:26 ` [PATCH net-next v3 00/47] [RFT] net: dpaa: Convert to phylink Camelia Alexandra Groza
2022-07-21 15:39 ` Sean Anderson
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