From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AF32C04A68 for ; Wed, 27 Jul 2022 12:46:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232422AbiG0MqF (ORCPT ); Wed, 27 Jul 2022 08:46:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231877AbiG0MqE (ORCPT ); Wed, 27 Jul 2022 08:46:04 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 4F94C13D6F; Wed, 27 Jul 2022 05:46:03 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A46CED6E; Wed, 27 Jul 2022 05:46:03 -0700 (PDT) Received: from bogus (unknown [10.57.11.51]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AE30B3F73B; Wed, 27 Jul 2022 05:46:00 -0700 (PDT) Date: Wed, 27 Jul 2022 13:45:56 +0100 From: Sudeep Holla To: Krzysztof Kozlowski Cc: Anup Patel , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Sudeep Holla , Daniel Lezcano , Thomas Gleixner , Andrew Jones , Atish Patra , Samuel Holland , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/2] dt-bindings: riscv: Add optional DT property riscv,timer-can-wake-cpu Message-ID: <20220727124556.owk3zlyzsg5uaa4t@bogus> References: <20220727114302.302201-1-apatel@ventanamicro.com> <20220727114302.302201-2-apatel@ventanamicro.com> <372e37bf-ac90-c371-ad9e-b9c18e1cc059@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <372e37bf-ac90-c371-ad9e-b9c18e1cc059@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Jul 27, 2022 at 02:07:50PM +0200, Krzysztof Kozlowski wrote: > On 27/07/2022 13:43, Anup Patel wrote: > > We add an optional DT property riscv,timer-can-wake-cpu which if present > > in CPU DT node then CPU timer is always powered-on and never loses context. > > > > Signed-off-by: Anup Patel > > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index d632ac76532e..b60b64b4113a 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -78,6 +78,12 @@ properties: > > - rv64imac > > - rv64imafdc > > > > + riscv,timer-can-wake-cpu: > > + type: boolean > > + description: > > + If present, the timer interrupt can wake up the CPU from > > + suspend/idle state. > > Isn't this a property of a timer, not CPU? IOW, your timer node should > have "wakeup-source" property. > I agree on the concept that this is property of the timer and not CPU. However we generally don't need to use wakeup-source property for timer as we ideally use this for waking up from system sleep state and we don't want to be running timer when we enter the state. > Now that's actual problem: why the RISC-V timer is bound to "riscv" > compatible, not to dedicated timer node? How is it related to actual CPU > (not SoC)? We have "always-on" property for this on arm arch timer, and I also see "regulator-always-on" or something similar defined. So in absence of timer node probably "local-timer-always-on" make sense ? Thoughts ? -- Regards, Sudeep