From: Rob Herring <robh@kernel.org>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Prabhakar <prabhakar.csengg@gmail.com>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH] dt-bindings: clock: renesas,rzg2l: Document RZ/Five SoC
Date: Wed, 27 Jul 2022 09:37:38 -0600 [thread overview]
Message-ID: <20220727153738.GA2696116-robh@kernel.org> (raw)
In-Reply-To: <20220726174525.620-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Tue, Jul 26, 2022 at 06:45:25PM +0100, Lad Prabhakar wrote:
> The CPG block on the RZ/Five SoC is almost identical to one found on the
> RZ/G2UL SoC. "renesas,r9a07g043-cpg" compatible string will be used on
> the RZ/Five SoC so to make this clear, update the comment to include
> RZ/Five SoC.
It's either the same part or it isn't. 'almost identical' doesn't sound
like the former. Unless it's the former, it's a nak for me.
Litering the drivers with #ifdef CONFIG_ARM64/CONFIG_RISCV is not great
either. That's not great for compile coverage and they have nothing to
do with the architecture.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> Note the driver changes [0] have been already queued for v5.20.
>
> [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/
> 20220622181723.13033-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> ---
> Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> index d036675e0779..487f74cdc749 100644
> --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> @@ -24,7 +24,7 @@ description: |
> properties:
> compatible:
> enum:
> - - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}
> + - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five
> - renesas,r9a07g044-cpg # RZ/G2{L,LC}
> - renesas,r9a07g054-cpg # RZ/V2L
> - renesas,r9a09g011-cpg # RZ/V2M
> --
> 2.17.1
>
>
next prev parent reply other threads:[~2022-07-27 15:37 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-26 17:45 [PATCH] dt-bindings: clock: renesas,rzg2l: Document RZ/Five SoC Lad Prabhakar
2022-07-27 15:37 ` Rob Herring [this message]
2022-08-12 8:47 ` Lad, Prabhakar
2022-08-12 9:32 ` Geert Uytterhoeven
2022-09-01 10:16 ` Geert Uytterhoeven
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