From: Sudip Mukherjee <sudip.mukherjee@sifive.com>
To: Serge Semin <fancer.lancer@gmail.com>,
Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: greentime.hu@sifive.com, jude.onyenegecha@sifive.com,
william.salmon@sifive.com, adnan.chowdhury@sifive.com,
ben.dooks@sifive.com, linux-spi@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
jeegar.lakhani@sifive.com,
Sudip Mukherjee <sudip.mukherjee@sifive.com>
Subject: [PATCH 05/11] spi: dw: define SPI_CTRLR0 register and its fields
Date: Tue, 2 Aug 2022 18:57:49 +0100 [thread overview]
Message-ID: <20220802175755.6530-6-sudip.mukherjee@sifive.com> (raw)
In-Reply-To: <20220802175755.6530-1-sudip.mukherjee@sifive.com>
Synopsys SSI controllers supporting enhanced SPI mode of operation has
SPI Control Register at offset 0xf4 which controls the following:
CLK_STRETCH_EN: Enables clock stretching capability in SPI transfers.
In case of write, if the FIFO becomes empty DWC_ssi will stretch the
clock until FIFO has enough data to continue the transfer. In case of
read, if the receive FIFO becomes full DWC_ssi will stop the clock until
data has been read from the FIFO.
WAIT_CYCLES: Wait cycles in Dual/Quad/Octal mode between control frames
transmit and data reception.
INST_L: Dual/Quad/Octal mode instruction length in bits.
ADDR_L: defines Length of Address to be transmitted.
For now, we are only using 32bit Address length and 8 bit Instruction
length.
Signed-off-by: Sudip Mukherjee <sudip.mukherjee@sifive.com>
---
drivers/spi/spi-dw.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index b8cc20e0deaa..a7a4637d6d32 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -63,6 +63,17 @@
#define DW_SPI_RX_SAMPLE_DLY 0xf0
#define DW_SPI_CS_OVERRIDE 0xf4
+/* Register offsets (Defined in DWC SSI 1.03a) */
+#define DW_HSSI_SPI_CTRLR0 0xf4
+
+/* Bit fields in SPI_CTRLR0 (Defined in DWC SSI 1.03a) */
+#define DW_HSSI_SPI_CTRLR0_CLK_STRETCH_EN BIT(30)
+#define DW_HSSI_SPI_CTRLR0_WAIT_CYCLE_MASK GENMASK(15, 11)
+#define DW_HSSI_SPI_CTRLR0_INST_L_MASK GENMASK(9, 8)
+#define DW_HSSI_SPI_CTRLR0_INST_L8 0x2
+#define DW_HSSI_SPI_CTRLR0_ADDR_L_MASK GENMASK(5, 2)
+#define DW_HSSI_SPI_CTRLR0_ADDR_L32 0x8
+
/* Bit fields in CTRLR0 (DWC APB SSI) */
#define DW_PSSI_CTRLR0_DFS_MASK GENMASK(3, 0)
#define DW_PSSI_CTRLR0_DFS32_MASK GENMASK(20, 16)
--
2.30.2
next prev parent reply other threads:[~2022-08-02 17:59 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-02 17:57 [PATCH 00/11] Add support for enhanced SPI for Designware SPI controllers Sudip Mukherjee
2022-08-02 17:57 ` [PATCH 01/11] spi: dw: define capability for enhanced spi Sudip Mukherjee
2022-08-02 18:47 ` Mark Brown
2022-08-03 17:34 ` Sudip Mukherjee
2022-08-03 17:40 ` Mark Brown
2022-08-26 18:16 ` Serge Semin
2022-08-02 17:57 ` [PATCH 02/11] spi: dw: add check for support of dual/quad/octal Sudip Mukherjee
2022-08-26 21:36 ` Serge Semin
2022-08-02 17:57 ` [PATCH 03/11] spi: dw: define spi_frf for dual/quad/octal modes Sudip Mukherjee
2022-08-26 22:03 ` Serge Semin
2022-08-26 22:22 ` Serge Semin
2022-08-02 17:57 ` [PATCH 04/11] spi: dw: use TMOD_RO to read in enhanced spi modes Sudip Mukherjee
2022-08-02 19:13 ` Mark Brown
2022-08-03 17:35 ` Sudip Mukherjee
2022-08-26 22:12 ` Serge Semin
2022-08-02 17:57 ` Sudip Mukherjee [this message]
2022-08-26 22:19 ` [PATCH 05/11] spi: dw: define SPI_CTRLR0 register and its fields Serge Semin
2022-08-02 17:57 ` [PATCH 06/11] spi: dw: update SPI_CTRLR0 register Sudip Mukherjee
2022-08-26 22:50 ` Serge Semin
2022-08-02 17:57 ` [PATCH 07/11] spi: dw: update NDF while writing in enhanced spi mode Sudip Mukherjee
2022-08-26 22:54 ` Serge Semin
2022-08-02 17:57 ` [PATCH 08/11] spi: dw: update buffer for " Sudip Mukherjee
2022-08-26 23:05 ` Serge Semin
2022-08-02 17:57 ` [PATCH 09/11] spi: dw: prepare the transfer routine for enhanced mode Sudip Mukherjee
2022-08-26 23:19 ` Serge Semin
2022-08-02 17:57 ` [PATCH 10/11] spi: dw-apb-ssi: add generic 1.03a version Sudip Mukherjee
2022-08-03 6:35 ` Krzysztof Kozlowski
2022-08-26 23:23 ` Serge Semin
2022-08-26 23:33 ` Serge Semin
2022-08-02 17:57 ` [PATCH 11/11] spi: dw: initialize dwc-ssi-1.03a controller Sudip Mukherjee
2022-08-26 23:31 ` Serge Semin
2022-08-03 18:56 ` [PATCH 00/11] Add support for enhanced SPI for Designware SPI controllers Serge Semin
2022-08-04 9:43 ` Sudip Mukherjee
2022-08-21 20:37 ` Serge Semin
2022-08-26 18:03 ` Serge Semin
2022-08-30 8:48 ` Sudip Mukherjee
2022-09-02 23:03 ` Serge Semin
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