From: Sudip Mukherjee <sudip.mukherjee@sifive.com>
To: Serge Semin <fancer.lancer@gmail.com>,
Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: greentime.hu@sifive.com, jude.onyenegecha@sifive.com,
william.salmon@sifive.com, adnan.chowdhury@sifive.com,
ben.dooks@sifive.com, linux-spi@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
jeegar.lakhani@sifive.com,
Sudip Mukherjee <sudip.mukherjee@sifive.com>
Subject: [PATCH 08/11] spi: dw: update buffer for enhanced spi mode
Date: Tue, 2 Aug 2022 18:57:52 +0100 [thread overview]
Message-ID: <20220802175755.6530-9-sudip.mukherjee@sifive.com> (raw)
In-Reply-To: <20220802175755.6530-1-sudip.mukherjee@sifive.com>
In enhanced spi mode we will be writing the address to a single FIFO
location instead of writing to multiple FIFOs in the standard SPI mode.
Save the cmd and address bytes in the buffer accordingly.
Signed-off-by: Sudip Mukherjee <sudip.mukherjee@sifive.com>
---
drivers/spi/spi-dw-core.c | 55 ++++++++++++++++++++++++++++++++++-----
1 file changed, 48 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
index 8cb30540ad5b..2564a2276572 100644
--- a/drivers/spi/spi-dw-core.c
+++ b/drivers/spi/spi-dw-core.c
@@ -520,7 +520,8 @@ static bool dw_spi_supports_mem_op(struct spi_mem *mem,
return spi_mem_default_supports_op(mem, op);
}
-static int dw_spi_init_mem_buf(struct dw_spi *dws, const struct spi_mem_op *op)
+static int dw_spi_init_mem_buf(struct dw_spi *dws, const struct spi_mem_op *op,
+ bool enhanced_spi)
{
unsigned int i, j, len;
u8 *out;
@@ -548,17 +549,57 @@ static int dw_spi_init_mem_buf(struct dw_spi *dws, const struct spi_mem_op *op)
*/
for (i = 0; i < op->cmd.nbytes; ++i)
out[i] = DW_SPI_GET_BYTE(op->cmd.opcode, op->cmd.nbytes - i - 1);
- for (j = 0; j < op->addr.nbytes; ++i, ++j)
- out[i] = DW_SPI_GET_BYTE(op->addr.val, op->addr.nbytes - j - 1);
- for (j = 0; j < op->dummy.nbytes; ++i, ++j)
- out[i] = 0x0;
+
+ if (enhanced_spi) {
+ /*
+ * Fill the remaining spaces of dws->reg_io_width bytes
+ * size register with zero for cmd.
+ */
+ for (; i < dws->reg_io_width; ++i)
+ out[i] = 0;
+ /*
+ * Copy the address bytes in dws->reg_io_width bytes size
+ * register and fill remaining spaces with zero.
+ */
+ for (j = op->addr.nbytes; j > 0; ++i, --j)
+ out[i] = DW_SPI_GET_BYTE(op->addr.val, op->addr.nbytes - j);
+ for (j = op->addr.nbytes; j < dws->reg_io_width; ++i, ++j)
+ out[i] = 0;
+ } else {
+ for (j = 0; j < op->addr.nbytes; ++i, ++j)
+ out[i] = DW_SPI_GET_BYTE(op->addr.val, op->addr.nbytes - j - 1);
+ }
+
+ if (!enhanced_spi) {
+ /*
+ * dummy bytes are not needed in enhanced mode as
+ * wait_cycles specified as number of SPI clock cycles
+ * between control frames transmit and data reception
+ * will be mentioned in enhanced spi mode.
+ */
+ for (j = 0; j < op->dummy.nbytes; ++i, ++j)
+ out[i] = 0x0;
+ }
if (op->data.dir == SPI_MEM_DATA_OUT)
memcpy(&out[i], op->data.buf.out, op->data.nbytes);
dws->n_bytes = 1;
dws->tx = out;
- dws->tx_len = len;
+
+ if (enhanced_spi) {
+ /*
+ * In enhanced mode cmd will be one FIFO and address
+ * will be one more FIFO.
+ */
+ dws->tx_len = 1;
+ if (op->addr.nbytes)
+ dws->tx_len += 1;
+ if (op->data.dir == SPI_MEM_DATA_OUT)
+ dws->tx_len += op->data.nbytes;
+ } else {
+ dws->tx_len = len;
+ }
if (op->data.dir == SPI_MEM_DATA_IN) {
dws->rx = op->data.buf.in;
dws->rx_len = op->data.nbytes;
@@ -744,7 +785,7 @@ static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
* Collect the outbound data into a single buffer to speed the
* transmission up at least on the initial stage.
*/
- ret = dw_spi_init_mem_buf(dws, op);
+ ret = dw_spi_init_mem_buf(dws, op, enhanced_spi);
if (ret)
return ret;
--
2.30.2
next prev parent reply other threads:[~2022-08-02 17:59 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-02 17:57 [PATCH 00/11] Add support for enhanced SPI for Designware SPI controllers Sudip Mukherjee
2022-08-02 17:57 ` [PATCH 01/11] spi: dw: define capability for enhanced spi Sudip Mukherjee
2022-08-02 18:47 ` Mark Brown
2022-08-03 17:34 ` Sudip Mukherjee
2022-08-03 17:40 ` Mark Brown
2022-08-26 18:16 ` Serge Semin
2022-08-02 17:57 ` [PATCH 02/11] spi: dw: add check for support of dual/quad/octal Sudip Mukherjee
2022-08-26 21:36 ` Serge Semin
2022-08-02 17:57 ` [PATCH 03/11] spi: dw: define spi_frf for dual/quad/octal modes Sudip Mukherjee
2022-08-26 22:03 ` Serge Semin
2022-08-26 22:22 ` Serge Semin
2022-08-02 17:57 ` [PATCH 04/11] spi: dw: use TMOD_RO to read in enhanced spi modes Sudip Mukherjee
2022-08-02 19:13 ` Mark Brown
2022-08-03 17:35 ` Sudip Mukherjee
2022-08-26 22:12 ` Serge Semin
2022-08-02 17:57 ` [PATCH 05/11] spi: dw: define SPI_CTRLR0 register and its fields Sudip Mukherjee
2022-08-26 22:19 ` Serge Semin
2022-08-02 17:57 ` [PATCH 06/11] spi: dw: update SPI_CTRLR0 register Sudip Mukherjee
2022-08-26 22:50 ` Serge Semin
2022-08-02 17:57 ` [PATCH 07/11] spi: dw: update NDF while writing in enhanced spi mode Sudip Mukherjee
2022-08-26 22:54 ` Serge Semin
2022-08-02 17:57 ` Sudip Mukherjee [this message]
2022-08-26 23:05 ` [PATCH 08/11] spi: dw: update buffer for " Serge Semin
2022-08-02 17:57 ` [PATCH 09/11] spi: dw: prepare the transfer routine for enhanced mode Sudip Mukherjee
2022-08-26 23:19 ` Serge Semin
2022-08-02 17:57 ` [PATCH 10/11] spi: dw-apb-ssi: add generic 1.03a version Sudip Mukherjee
2022-08-03 6:35 ` Krzysztof Kozlowski
2022-08-26 23:23 ` Serge Semin
2022-08-26 23:33 ` Serge Semin
2022-08-02 17:57 ` [PATCH 11/11] spi: dw: initialize dwc-ssi-1.03a controller Sudip Mukherjee
2022-08-26 23:31 ` Serge Semin
2022-08-03 18:56 ` [PATCH 00/11] Add support for enhanced SPI for Designware SPI controllers Serge Semin
2022-08-04 9:43 ` Sudip Mukherjee
2022-08-21 20:37 ` Serge Semin
2022-08-26 18:03 ` Serge Semin
2022-08-30 8:48 ` Sudip Mukherjee
2022-09-02 23:03 ` Serge Semin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220802175755.6530-9-sudip.mukherjee@sifive.com \
--to=sudip.mukherjee@sifive.com \
--cc=adnan.chowdhury@sifive.com \
--cc=ben.dooks@sifive.com \
--cc=broonie@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=fancer.lancer@gmail.com \
--cc=greentime.hu@sifive.com \
--cc=jeegar.lakhani@sifive.com \
--cc=jude.onyenegecha@sifive.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=william.salmon@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).