From: Jagan Teki <jagan@edgeble.ai>
To: Heiko Stuebner <heiko@sntech.de>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Kever Yang <kever.yang@rock-chips.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
Jagan Teki <jagan@edgeble.ai>
Subject: [PATCH v3 14/19] ARM: dts: rockchip: Add Rockchip RV1126 pinctrl
Date: Thu, 18 Aug 2022 18:11:27 +0530 [thread overview]
Message-ID: <20220818124132.125304-15-jagan@edgeble.ai> (raw)
In-Reply-To: <20220818124132.125304-1-jagan@edgeble.ai>
Add pinctrl definitions for Rockchip RV1126 and the pinctrl
conf's are included it from arm64 rockchip devicetree path.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Changes for v3:
- none
Changes for v2:
- spilt pinctrl as separate patch
MAINTAINERS | 2 +-
arch/arm/boot/dts/rv1126-pinctrl.dtsi | 302 ++++++++++++++++++++++++++
2 files changed, 303 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/rv1126-pinctrl.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index f679152bdbad..124247f95787 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2646,7 +2646,7 @@ F: Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
F: Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
F: Documentation/devicetree/bindings/spi/spi-rockchip.yaml
F: arch/arm/boot/dts/rk3*
-F: arch/arm/boot/dts/rv1108*
+F: arch/arm/boot/dts/rv11*
F: arch/arm/mach-rockchip/
F: drivers/*/*/*rockchip*
F: drivers/*/*rockchip*
diff --git a/arch/arm/boot/dts/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rv1126-pinctrl.dtsi
new file mode 100644
index 000000000000..1c46c5042221
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126-pinctrl.dtsi
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <arm64/rockchip/rockchip-pinconf.dtsi>
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+ emmc {
+ /omit-if-no-ref/
+ emmc_rstnout: emmc-rstnout {
+ rockchip,pins =
+ /* emmc_rstn */
+ <1 RK_PA3 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins =
+ /* emmc_d0 */
+ <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d1 */
+ <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d2 */
+ <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d3 */
+ <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d4 */
+ <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d5 */
+ <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d6 */
+ <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d7 */
+ <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ emmc_clk: emmc-clk {
+ rockchip,pins =
+ /* emmc_clko */
+ <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ emmc_cmd: emmc-cmd {
+ rockchip,pins =
+ /* emmc_cmd */
+ <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
+ };
+ };
+ i2c0 {
+ /omit-if-no-ref/
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins =
+ /* i2c0_scl */
+ <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c0_sda */
+ <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ i2c1 {
+ /omit-if-no-ref/
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins =
+ /* i2c1_scl */
+ <1 RK_PD3 1 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c1_sda */
+ <1 RK_PD2 1 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ i2c2 {
+ /omit-if-no-ref/
+ i2c2_xfer: i2c2-xfer {
+ rockchip,pins =
+ /* i2c2_scl */
+ <0 RK_PC2 1 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c2_sda */
+ <0 RK_PC3 1 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ i2c3 {
+ /omit-if-no-ref/
+ i2c3m0_xfer: i2c3m0-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m0 */
+ <3 RK_PA4 5 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c3_sda_m0 */
+ <3 RK_PA5 5 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ /omit-if-no-ref/
+ i2c3m1_xfer: i2c3m1-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m1 */
+ <2 RK_PD4 7 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c3_sda_m1 */
+ <2 RK_PD5 7 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ /omit-if-no-ref/
+ i2c3m2_xfer: i2c3m2-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m2 */
+ <1 RK_PD6 3 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c3_sda_m2 */
+ <1 RK_PD7 3 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ i2c4 {
+ /omit-if-no-ref/
+ i2c4m0_xfer: i2c4m0-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m0 */
+ <3 RK_PA0 7 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c4_sda_m0 */
+ <3 RK_PA1 7 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ /omit-if-no-ref/
+ i2c4m1_xfer: i2c4m1-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m1 */
+ <4 RK_PA0 4 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c4_sda_m1 */
+ <4 RK_PA1 4 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ i2c5 {
+ /omit-if-no-ref/
+ i2c5m0_xfer: i2c5m0-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m0 */
+ <2 RK_PA5 7 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c5_sda_m0 */
+ <2 RK_PB3 7 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ /omit-if-no-ref/
+ i2c5m1_xfer: i2c5m1-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m1 */
+ <3 RK_PB0 5 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c5_sda_m1 */
+ <3 RK_PB1 5 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ /omit-if-no-ref/
+ i2c5m2_xfer: i2c5m2-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m2 */
+ <1 RK_PD0 4 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c5_sda_m2 */
+ <1 RK_PD1 4 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ sdmmc0 {
+ /omit-if-no-ref/
+ sdmmc0_bus4: sdmmc0-bus4 {
+ rockchip,pins =
+ /* sdmmc0_d0 */
+ <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d1 */
+ <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d2 */
+ <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d3 */
+ <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_clk: sdmmc0-clk {
+ rockchip,pins =
+ /* sdmmc0_clk */
+ <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_cmd: sdmmc0-cmd {
+ rockchip,pins =
+ /* sdmmc0_cmd */
+ <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_det: sdmmc0-det {
+ rockchip,pins =
+ <0 RK_PA3 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_pwr: sdmmc0-pwr {
+ rockchip,pins =
+ <0 RK_PC0 1 &pcfg_pull_none>;
+ };
+ };
+ sdmmc1 {
+ /omit-if-no-ref/
+ sdmmc1_bus4: sdmmc1-bus4 {
+ rockchip,pins =
+ /* sdmmc1_d0 */
+ <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d1 */
+ <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d2 */
+ <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d3 */
+ <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_clk: sdmmc1-clk {
+ rockchip,pins =
+ /* sdmmc1_clk */
+ <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_cmd: sdmmc1-cmd {
+ rockchip,pins =
+ /* sdmmc1_cmd */
+ <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_det: sdmmc1-det {
+ rockchip,pins =
+ <1 RK_PD0 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_pwr: sdmmc1-pwr {
+ rockchip,pins =
+ <1 RK_PD1 2 &pcfg_pull_none>;
+ };
+ };
+ uart0 {
+ /omit-if-no-ref/
+ uart0_xfer: uart0-xfer {
+ rockchip,pins =
+ /* uart0_rx */
+ <1 RK_PC2 1 &pcfg_pull_up>,
+ /* uart0_tx */
+ <1 RK_PC3 1 &pcfg_pull_up>;
+ };
+ /omit-if-no-ref/
+ uart0_ctsn: uart0-ctsn {
+ rockchip,pins =
+ <1 RK_PC1 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart0_rtsn: uart0-rtsn {
+ rockchip,pins =
+ <1 RK_PC0 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart0_rtsn_gpio: uart0-rts-pin {
+ rockchip,pins =
+ <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+ uart1 {
+ /omit-if-no-ref/
+ uart1m0_xfer: uart1m0-xfer {
+ rockchip,pins =
+ /* uart1_rx_m0 */
+ <0 RK_PB7 2 &pcfg_pull_up>,
+ /* uart1_tx_m0 */
+ <0 RK_PB6 2 &pcfg_pull_up>;
+ };
+ };
+ uart2 {
+ /omit-if-no-ref/
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins =
+ /* uart2_rx_m1 */
+ <3 RK_PA3 1 &pcfg_pull_up>,
+ /* uart2_tx_m1 */
+ <3 RK_PA2 1 &pcfg_pull_up>;
+ };
+ };
+ uart3 {
+ /omit-if-no-ref/
+ uart3m0_xfer: uart3m0-xfer {
+ rockchip,pins =
+ /* uart3_rx_m0 */
+ <3 RK_PC7 4 &pcfg_pull_up>,
+ /* uart3_tx_m0 */
+ <3 RK_PC6 4 &pcfg_pull_up>;
+ };
+ };
+ uart4 {
+ /omit-if-no-ref/
+ uart4m0_xfer: uart4m0-xfer {
+ rockchip,pins =
+ /* uart4_rx_m0 */
+ <3 RK_PA5 4 &pcfg_pull_up>,
+ /* uart4_tx_m0 */
+ <3 RK_PA4 4 &pcfg_pull_up>;
+ };
+ };
+ uart5 {
+ /omit-if-no-ref/
+ uart5m0_xfer: uart5m0-xfer {
+ rockchip,pins =
+ /* uart5_rx_m0 */
+ <3 RK_PA7 4 &pcfg_pull_up>,
+ /* uart5_tx_m0 */
+ <3 RK_PA6 4 &pcfg_pull_up>;
+ };
+ };
+};
--
2.25.1
next prev parent reply other threads:[~2022-08-18 12:42 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-18 12:41 [PATCH v3 00/19] ARM: Add Rockchip RV1126 support Jagan Teki
2022-08-18 12:41 ` [PATCH v3 01/19] dt-bindings: power: Add power-domain header for RV1126 Jagan Teki
2022-08-19 12:25 ` Krzysztof Kozlowski
2022-08-18 12:41 ` [PATCH v3 02/19] dt-bindings: power: rockchip: Document RV1126 power-controller Jagan Teki
2022-08-18 12:41 ` [PATCH v3 03/19] soc: rockchip: power-domain: Add RV1126 power domains Jagan Teki
2022-08-18 12:41 ` [PATCH v3 04/19] dt-bindings: power: rockchip: Document RV1126 PMU IO domains Jagan Teki
2022-08-18 12:41 ` [PATCH v3 05/19] soc: rockchip: io-domain: Add RV1126 " Jagan Teki
2022-08-18 12:41 ` [PATCH v3 06/19] dt-bindings: pinctrl: rockchip: Document RV1126 pinctrl Jagan Teki
2022-08-22 7:50 ` Linus Walleij
2022-08-18 12:41 ` [PATCH v3 07/19] pinctrl: rockchip: Add RV1126 pinctrl support Jagan Teki
2022-08-22 7:51 ` Linus Walleij
2022-08-18 12:41 ` [PATCH v3 08/19] clk: rockchip: Add MUXTBL variant Jagan Teki
2022-08-18 12:41 ` [PATCH v3 09/19] clk: rockchip: Add dt-binding header for RV1126 Jagan Teki
2022-08-22 18:10 ` Rob Herring
2022-08-23 12:57 ` Jagan Teki
2022-08-23 17:56 ` Heiko Stübner
2022-09-05 5:27 ` Jagan Teki
2022-09-05 16:37 ` Krzysztof Kozlowski
2022-08-18 12:41 ` [PATCH v3 10/19] dt-bindings: clock: rockchip: Document RV1126 CRU Jagan Teki
2022-08-18 21:29 ` Stephen Boyd
2022-08-19 21:20 ` Jagan Teki
2022-08-23 17:59 ` Heiko Stübner
2022-08-18 12:41 ` [PATCH v3 11/19] Add clock controller support for RV1126 SoC Jagan Teki
2022-08-18 12:41 ` [PATCH v3 12/19] dt-bindings: soc: rockchip: Document RV1126 grf Jagan Teki
2022-08-18 12:41 ` [PATCH v3 13/19] dt-bindings: soc: rockchip: Document RV1126 pmugrf Jagan Teki
2022-08-18 12:41 ` Jagan Teki [this message]
2022-08-18 12:41 ` [PATCH v3 15/19] ARM: dts: rockchip: Add Rockchip RV1126 SoC Jagan Teki
2022-08-18 12:41 ` [PATCH v3 16/19] dt-bindings: vendor-prefixes: Add Edgeble AI Technologies Pvt. Ltd Jagan Teki
2022-08-18 12:41 ` [PATCH v3 17/19] dt-bindings: arm: rockchip: Add Edgeble AI Edge Compute Module 0 Carrier Jagan Teki
2022-08-18 12:41 ` [PATCH v3 18/19] ARM: dts: rockchip: rv1126: Add Edgeble AI Edge Compute Module 0 Jagan Teki
2022-08-18 12:41 ` [PATCH v3 19/19] ARM: dts: rockchip: rv1126: Add Edgeble AI Edge Compute Module 0 Carrier Jagan Teki
2022-09-05 9:58 ` (subset) [PATCH v3 00/19] ARM: Add Rockchip RV1126 support Heiko Stuebner
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