From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91FF4C28B2B for ; Thu, 18 Aug 2022 12:42:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244697AbiHRMmP (ORCPT ); Thu, 18 Aug 2022 08:42:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244458AbiHRMmO (ORCPT ); Thu, 18 Aug 2022 08:42:14 -0400 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 777A3B24AB for ; Thu, 18 Aug 2022 05:42:12 -0700 (PDT) Received: by mail-pl1-x62b.google.com with SMTP id 2so1437974pll.0 for ; Thu, 18 Aug 2022 05:42:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=edgeble-ai.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=8Nkr7r66XIhVJb7JyEDPde3ucJLUnXz87S1YILChFSQ=; b=QhlCAvnMGaAFH9I+lhJhXHK/6f2Re+rxeGvx2G57tBFypGU+mgkZDgioqX8jPtf0jo UOR3NPSctgfd0wawJO09GaldVxOTQoAYLncDdTRjYDX+RbjpWL3/OVM56UFJyIwnqzIC JR+BTWigiDjkGynETEMao0VurDg2z5Fp4cUS1Owy0PhO8GYNl5FtvAk8Zf+cdpxCcFYW 5I8fcoQi5J27Hruzb70UqiSTyz4y03asGj95azyWLynjnnaCel2K1alSgX4RUBQzHCnd i8STEtZ5LoLfUN6rU+ZPDSwjVIcjrHPK9tHCWEWHZIpVDvme/xj3TbQ4V+tguG45AhzY eHtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=8Nkr7r66XIhVJb7JyEDPde3ucJLUnXz87S1YILChFSQ=; b=FJBbiDTEY6EfeeVggKJNDWUfsW/30h+2kAM6hGQuGqm5zSj0R0oRU/q4KzvJvveufd 23R5aiS5LjQ71OzpzBBZwZLId+ldGIgwCFR4Z13pOwCDx2SzcmXLb5NzAX8gKwvc9NmB 3hgDoVyy4E2hMmlQW37hUSWYcvu2ifiPs7ew30oKxq+vy7/xf7zk6Up5G1GOOCDGSt/6 MvjrckWOV7LsVJCYQfYLwv3BipfLayoo7uEOOXgCz8vl+iKcOvPDWg1w4+qXBL0D4Ss4 +B5TaEg6GsrHG3RyIa7c3huCh3zZxxAmtp//cqS4pWoaWFz0upEtR0eTFX99NVEF31KO mKtA== X-Gm-Message-State: ACgBeo1cdLy3nTdQrCimQxUO+vUcaEgVShVA9r0Ur0mPLSp+cVClv2IE CDepx6MBShm4sDjh2XAPITVRRw== X-Google-Smtp-Source: AA6agR5g6VQ7ytP8lPjIJRRm4hvrTa1bnjV0idGre8DRaMeEWEwe69JjGUbNdQgZaieeC7FceleYPg== X-Received: by 2002:a17:90b:198a:b0:1f5:2f97:12a0 with SMTP id mv10-20020a17090b198a00b001f52f9712a0mr2840938pjb.97.1660826532058; Thu, 18 Aug 2022 05:42:12 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c00a:a073:d1c4:8ea9:aedc:add1]) by smtp.gmail.com with ESMTPSA id x6-20020aa78f06000000b005302cef1684sm1495651pfr.34.2022.08.18.05.42.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Aug 2022 05:42:11 -0700 (PDT) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Kever Yang Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, Elaine Zhang , linux-clk@vger.kernel.org, Michael Turquette , Stephen Boyd , Jagan Teki Subject: [PATCH v3 08/19] clk: rockchip: Add MUXTBL variant Date: Thu, 18 Aug 2022 18:11:21 +0530 Message-Id: <20220818124132.125304-9-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818124132.125304-1-jagan@edgeble.ai> References: <20220818124132.125304-1-jagan@edgeble.ai> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Elaine Zhang A clock branch consisting of a mux with non-standard select values. The parent in Mux table is sorted by priority. Cc: linux-clk@vger.kernel.org Cc: Michael Turquette Cc: Stephen Boyd Signed-off-by: Elaine Zhang Signed-off-by: Jagan Teki --- Changes for v3, v2: - none drivers/clk/rockchip/clk.c | 27 +++++++++++++++++++++------ drivers/clk/rockchip/clk.h | 17 +++++++++++++++++ 2 files changed, 38 insertions(+), 6 deletions(-) diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index bb8a844309bf..e63d4f20b479 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -40,6 +40,7 @@ static struct clk *rockchip_clk_register_branch(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, + u32 *mux_table, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, @@ -62,6 +63,7 @@ static struct clk *rockchip_clk_register_branch(const char *name, mux->shift = mux_shift; mux->mask = BIT(mux_width) - 1; mux->flags = mux_flags; + mux->table = mux_table; mux->lock = lock; mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops : &clk_mux_ops; @@ -270,6 +272,8 @@ static struct clk *rockchip_clk_register_frac_branch( frac_mux->shift = child->mux_shift; frac_mux->mask = BIT(child->mux_width) - 1; frac_mux->flags = child->mux_flags; + if (child->mux_table) + frac_mux->table = child->mux_table; frac_mux->lock = lock; frac_mux->hw.init = &init; @@ -444,11 +448,21 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, /* catch simple muxes */ switch (list->branch_type) { case branch_mux: - clk = clk_register_mux(NULL, list->name, - list->parent_names, list->num_parents, - flags, ctx->reg_base + list->muxdiv_offset, - list->mux_shift, list->mux_width, - list->mux_flags, &ctx->lock); + if (list->mux_table) + clk = clk_register_mux_table(NULL, list->name, + list->parent_names, list->num_parents, + flags, + ctx->reg_base + list->muxdiv_offset, + list->mux_shift, list->mux_width, + list->mux_flags, list->mux_table, + &ctx->lock); + else + clk = clk_register_mux(NULL, list->name, + list->parent_names, list->num_parents, + flags, + ctx->reg_base + list->muxdiv_offset, + list->mux_shift, list->mux_width, + list->mux_flags, &ctx->lock); break; case branch_muxgrf: clk = rockchip_clk_register_muxgrf(list->name, @@ -506,7 +520,8 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, ctx->reg_base, list->muxdiv_offset, list->mux_shift, list->mux_width, list->mux_flags, - list->div_offset, list->div_shift, list->div_width, + list->mux_table, list->div_offset, + list->div_shift, list->div_width, list->div_flags, list->div_table, list->gate_offset, list->gate_shift, list->gate_flags, flags, &ctx->lock); diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 7aa45cc70287..93937fb1d368 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -448,6 +448,7 @@ struct rockchip_clk_branch { u8 mux_shift; u8 mux_width; u8 mux_flags; + u32 *mux_table; int div_offset; u8 div_shift; u8 div_width; @@ -680,6 +681,22 @@ struct rockchip_clk_branch { .gate_offset = -1, \ } +#define MUXTBL(_id, cname, pnames, f, o, s, w, mf, mt) \ + { \ + .id = _id, \ + .branch_type = branch_mux, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = f, \ + .muxdiv_offset = o, \ + .mux_shift = s, \ + .mux_width = w, \ + .mux_flags = mf, \ + .gate_offset = -1, \ + .mux_table = mt, \ + } + #define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \ { \ .id = _id, \ -- 2.25.1