From: "Nícolas F. R. A. Prado" <nfraprado@collabora.com>
To: "Nancy.Lin" <nancy.lin@mediatek.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
wim@linux-watchdog.org,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
linux@roeck-us.net, David Airlie <airlied@linux.ie>,
Daniel Vetter <daniel@ffwll.ch>,
Nathan Chancellor <nathan@kernel.org>,
Nick Desaulniers <ndesaulniers@google.com>,
"jason-jh . lin" <jason-jh.lin@mediatek.com>,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
dri-devel@lists.freedesktop.org, llvm@lists.linux.dev,
singo.chang@mediatek.com,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH v25 07/10] soc: mediatek: mmsys: add mmsys for support 64 reset bits
Date: Fri, 19 Aug 2022 10:25:22 -0400 [thread overview]
Message-ID: <20220819142522.c4o3nrkxfj2r3zd7@notapiano> (raw)
In-Reply-To: <12062a2e2957113d40b4bf3c1c62d18418b51a12.camel@mediatek.com>
On Fri, Aug 19, 2022 at 12:13:23PM +0800, Nancy.Lin wrote:
> Hi Nicolas,
>
>
> On Fri, 2022-08-19 at 10:09 +0800, Nancy.Lin wrote:
> > Hi Nicolas,
> >
> > Thanks for the review.
> >
> > On Thu, 2022-08-18 at 17:47 -0400, Nícolas F. R. A. Prado wrote:
> > > Hi Nancy,
> > >
> > > On Mon, Jul 11, 2022 at 03:52:42PM +0800, Nancy.Lin wrote:
> > > [..]
> > > > static const struct mtk_mmsys_driver_data
> > > > mt2701_mmsys_driver_data
> > > > = {
> > > > .clk_driver = "clk-mt2701-mm",
> > > > .routes = mmsys_default_routing_table,
> > > > @@ -86,6 +88,7 @@ static const struct mtk_mmsys_driver_data
> > > > mt8173_mmsys_driver_data = {
> > > > .routes = mmsys_default_routing_table,
> > > > .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> > > > .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> > > > + .num_resets = 32,
> > > > };
> > > >
> > > > static const struct mtk_mmsys_match_data mt8173_mmsys_match_data
> > > > =
> > > > {
> > > > @@ -100,6 +103,7 @@ static const struct mtk_mmsys_driver_data
> > > > mt8183_mmsys_driver_data = {
> > > > .routes = mmsys_mt8183_routing_table,
> > > > .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> > > > .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> > > > + .num_resets = 32,
> > > > };
> > > >
> > > > static const struct mtk_mmsys_match_data mt8183_mmsys_match_data
> > > > =
> > > > {
> > > > @@ -114,6 +118,7 @@ static const struct mtk_mmsys_driver_data
> > > > mt8186_mmsys_driver_data = {
> > > > .routes = mmsys_mt8186_routing_table,
> > > > .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
> > > > .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
> > > > + .num_resets = 32,
> > > > };
> > >
> > > [..]
> > > > @@ -351,18 +362,6 @@ static int mtk_mmsys_probe(struct
> > > > platform_device *pdev)
> > > > return ret;
> > > > }
> > > >
> > > > - spin_lock_init(&mmsys->lock);
> > > > -
> > > > - mmsys->rcdev.owner = THIS_MODULE;
> > > > - mmsys->rcdev.nr_resets = 32;
> > >
> > > The number of resets was previously always set to 32, and now
> > > you're
> > > instead
> > > setting it based on num_resets from each machine. The issue is,
> > > you're
> > > forgetting a bunch of them.
> > >
> > > mt8192 didn't get a num_reset, so this commit breaks the display on
> > > mt8192 based
> > > devices. But mt8192 isn't the only one, there are other platforms
> > > missing this
> > > property. Please set num_resets to 32 in every single one of them,
> > > otherwise
> > > there will be display regressions.
> > >
> > > Thanks,
> > > Nícolas
> >
> > It's my mistake. I will set num_resets to 32 for every mmsys driver.
> >
> > Thanks,
> > Nancy
>
> After review the code, I think only the mmsys driver with the
> sw0_rst_offset setting should set num_resets to 32, otherwise it would
> set wrong addr in the mtk_mmsys_reset_update() function. Those mmsys
> without sw0_rst_offset set should not set num_resets to 32.
I don't think that's the case. num_resets and sw0_rst_offset are completely
unrelated in the code. sw0_rst_offset just gives the offset from the base
mmsys memory to the register that manages resets; it can be 0 in which case the
reset register would be right at the start of the mmsys iospace.
nr_resets, which is set by num_resets, on the other hand, seems to be used in a
single place: of_reset_simple_xlate() in drivers/reset/core.c. And the logic
there is really simple: if you pass a reset id greater than nr_resets, you will
get an error. So when you leave num_resets unset (0) for any of the platforms,
you're making all reset registrations in the DT fail.
So I'm really confident that we need num_resets = 32 on *all* platforms (except
the ones that have 64 of course, we just can't leave them empty).
Thanks,
Nícolas
next prev parent reply other threads:[~2022-08-19 14:25 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20220711075245.10492-1-nancy.lin@mediatek.com>
[not found] ` <20220711075245.10492-8-nancy.lin@mediatek.com>
2022-08-18 21:47 ` [PATCH v25 07/10] soc: mediatek: mmsys: add mmsys for support 64 reset bits Nícolas F. R. A. Prado
[not found] ` <d7ccb3fb2630c1c0b6dda2990cff72169e5e5d0b.camel@mediatek.com>
[not found] ` <12062a2e2957113d40b4bf3c1c62d18418b51a12.camel@mediatek.com>
2022-08-19 14:25 ` Nícolas F. R. A. Prado [this message]
[not found] ` <0afc69a72a4c55b17f8b626d43a08ad56ada64c5.camel@mediatek.com>
2022-08-18 21:59 ` [PATCH v25 00/10] Add MediaTek SoC(vdosys1) support for mt8195 Nícolas F. R. A. Prado
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