Re: [PATCH v2 1/2] dt-bindings: clock: add QCOM SM6115 display clock bindings

[Rob Herring <robh@kernel.org>]

On Fri, Aug 19, 2022 at 10:12:21PM +0200, Adam Skladowski wrote:
> Add device tree bindings for display clock controller for
> Qualcomm Technology Inc's SM6115 SoC.
> 
> Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
> ---
>  .../bindings/clock/qcom,sm6115-dispcc.yaml    | 88 +++++++++++++++++++
>  .../dt-bindings/clock/qcom,sm6115-dispcc.h    | 36 ++++++++
>  2 files changed, 124 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6115-dispcc.yaml
>  create mode 100644 include/dt-bindings/clock/qcom,sm6115-dispcc.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-dispcc.yaml
> new file mode 100644
> index 000000000000..c9b97281171c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-dispcc.yaml
> @@ -0,0 +1,88 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,sm6115-dispcc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Display Clock Controller Binding for SM6115
> +
> +maintainers:
> +  - Bjorn Andersson <bjorn.andersson@linaro.org>

As of today, bouncing...

Otherwise, looks fine.

> +
> +description: |
> +  Qualcomm display clock control module which supports the clocks and
> +  power domains on SM6115.
> +
> +  See also:
> +    dt-bindings/clock/qcom,sm6115-dispcc.h
> +
> +properties:
> +  compatible:
> +    enum:
> +      - qcom,sm6115-dispcc
> +
> +  clocks:
> +    items:
> +      - description: Board XO source
> +      - description: Byte clock from DSI PHY0
> +      - description: Pixel clock from DSI PHY0
> +      - description: GPLL0 clock from GCC
> +      - description: GPLL0 div clock from GCC
> +      - description: Board sleep clock
> +
> +  clock-names:
> +    items:
> +      - const: bi_tcxo
> +      - const: dsi0_phy_pll_out_byteclk
> +      - const: dsi0_phy_pll_out_dsiclk
> +      - const: gcc_disp_gpll0_clk_src
> +      - const: gcc_disp_gpll0_div_clk_src
> +      - const: sleep_clk
> +
> +  '#clock-cells':
> +    const: 1
> +
> +  '#reset-cells':
> +    const: 1
> +
> +  '#power-domain-cells':
> +    const: 1
> +
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - '#clock-cells'
> +  - '#reset-cells'
> +  - '#power-domain-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,rpmcc.h>
> +    #include <dt-bindings/clock/qcom,gcc-sm6115.h>
> +    clock-controller@5f00000 {
> +      compatible = "qcom,sm6115-dispcc";
> +      reg = <0x5f00000 0x20000>;
> +      clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
> +               <&dsi0_phy 0>,
> +               <&dsi0_phy 1>,
> +               <&gcc GCC_DISP_GPLL0_CLK_SRC>,
> +               <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
> +               <&sleep_clk>;
> +      clock-names = "bi_tcxo",
> +                    "dsi0_phy_pll_out_byteclk",
> +                    "dsi0_phy_pll_out_dsiclk",
> +                    "gcc_disp_gpll0_clk_src",
> +                    "gcc_disp_gpll0_div_clk_src",
> +                    "sleep_clk";
> +      #clock-cells = <1>;
> +      #reset-cells = <1>;
> +      #power-domain-cells = <1>;
> +    };
> +...
> diff --git a/include/dt-bindings/clock/qcom,sm6115-dispcc.h b/include/dt-bindings/clock/qcom,sm6115-dispcc.h
> new file mode 100644
> index 000000000000..d1a6c45b5029
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,sm6115-dispcc.h
> @@ -0,0 +1,36 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2022, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H
> +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H
> +
> +/* DISP_CC clocks */
> +#define DISP_CC_PLL0			0
> +#define DISP_CC_PLL0_OUT_MAIN		1
> +#define DISP_CC_MDSS_AHB_CLK		2
> +#define DISP_CC_MDSS_AHB_CLK_SRC	3
> +#define DISP_CC_MDSS_BYTE0_CLK		4
> +#define DISP_CC_MDSS_BYTE0_CLK_SRC	5
> +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC	6
> +#define DISP_CC_MDSS_BYTE0_INTF_CLK	7
> +#define DISP_CC_MDSS_ESC0_CLK		8
> +#define DISP_CC_MDSS_ESC0_CLK_SRC	9
> +#define DISP_CC_MDSS_MDP_CLK		10
> +#define DISP_CC_MDSS_MDP_CLK_SRC	11
> +#define DISP_CC_MDSS_MDP_LUT_CLK	12
> +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK	13
> +#define DISP_CC_MDSS_PCLK0_CLK		14
> +#define DISP_CC_MDSS_PCLK0_CLK_SRC	15
> +#define DISP_CC_MDSS_ROT_CLK		16
> +#define DISP_CC_MDSS_ROT_CLK_SRC	17
> +#define DISP_CC_MDSS_VSYNC_CLK		18
> +#define DISP_CC_MDSS_VSYNC_CLK_SRC	19
> +#define DISP_CC_SLEEP_CLK		20
> +#define DISP_CC_SLEEP_CLK_SRC		21
> +
> +/* DISP_CC GDSCR */
> +#define MDSS_GDSC			0
> +
> +#endif
> -- 
> 2.25.1
> 
>