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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id c7-20020a056870c08700b00118927e0dacsm3212873oad.4.2022.08.22.14.41.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 14:41:28 -0700 (PDT) Received: (nullmailer pid 903367 invoked by uid 1000); Mon, 22 Aug 2022 21:41:26 -0000 Date: Mon, 22 Aug 2022 16:41:26 -0500 From: Rob Herring To: Siddharth Vadapalli Cc: lee.jones@linaro.org, krzysztof.kozlowski@linaro.org, krzysztof.kozlowski+dt@linaro.org, kishon@ti.com, vkoul@kernel.org, dan.carpenter@oracle.com, grygorii.strashko@ti.com, rogerq@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: Re: [PATCH v3 1/2] dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J7200 Message-ID: <20220822214126.GA896562-robh@kernel.org> References: <20220822065631.27933-1-s-vadapalli@ti.com> <20220822065631.27933-2-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220822065631.27933-2-s-vadapalli@ti.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Aug 22, 2022 at 12:26:30PM +0530, Siddharth Vadapalli wrote: > TI's J7200 SoC supports additional PHY modes like QSGMII and SGMII > that are not supported on earlier SoCs. Add a compatible for it. > > Signed-off-by: Siddharth Vadapalli > --- > .../mfd/ti,j721e-system-controller.yaml | 6 ++++ > .../bindings/phy/ti,phy-gmii-sel.yaml | 30 ++++++++++++++++++- > 2 files changed, 35 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml > index 73cffc45e056..466724cb4157 100644 > --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml > +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml > @@ -54,6 +54,12 @@ patternProperties: > description: > Clock provider for TI EHRPWM nodes. > > + "phy@[0-9a-f]+$": > + type: object > + $ref: ../phy/ti,phy-gmii-sel.yaml /schemas/phy/... > + description: > + This is the register to set phy mode through phy-gmii-sel driver. > + > required: > - compatible > - reg > diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml > index ff8a6d9eb153..0ffb97f1a77c 100644 > --- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml > +++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml > @@ -53,12 +53,24 @@ properties: > - ti,am43xx-phy-gmii-sel > - ti,dm814-phy-gmii-sel > - ti,am654-phy-gmii-sel > + - ti,j7200-cpsw5g-phy-gmii-sel > > reg: > maxItems: 1 > > '#phy-cells': true > > + ti,qsgmii-main-ports: > + $ref: /schemas/types.yaml#/definitions/uint32-array > + description: | > + Required only for QSGMII mode. Array to select the port for > + QSGMII main mode. Rest of the ports are selected as QSGMII_SUB > + ports automatically. Any one of the 4 CPSW5G ports can act as the > + main port with the rest of them being the QSGMII_SUB ports. > + items: > + minimum: 1 > + maximum: 4 > + > allOf: > - if: > properties: > @@ -73,6 +85,22 @@ allOf: > '#phy-cells': > const: 1 > description: CPSW port number (starting from 1) > + - if: > + properties: > + compatible: > + contains: > + enum: > + - ti,j7200-cpsw5g-phy-gmii-sel > + then: > + properties: > + '#phy-cells': > + const: 1 > + description: CPSW port number (starting from 1) > + ti,qsgmii-main-ports: > + maxItems: 1 If the array size can only ever be 1, then it's a uint32, not a uint32-array. > + else: > + properties: > + ti,qsgmii-main-ports: false > - if: > properties: > compatible: > @@ -97,7 +125,7 @@ additionalProperties: false > > examples: > - | > - phy_gmii_sel: phy-gmii-sel@650 { > + phy_gmii_sel: phy@650 { > compatible = "ti,am3352-phy-gmii-sel"; > reg = <0x650 0x4>; > #phy-cells = <2>; > -- > 2.25.1 > >