From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 693DDC04AA5 for ; Wed, 24 Aug 2022 22:37:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230135AbiHXWhP (ORCPT ); Wed, 24 Aug 2022 18:37:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230089AbiHXWhN (ORCPT ); Wed, 24 Aug 2022 18:37:13 -0400 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB1F374CE0; Wed, 24 Aug 2022 15:37:11 -0700 (PDT) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 1DC372014B8; Thu, 25 Aug 2022 00:37:10 +0200 (CEST) Received: from smtp.na-rdc02.nxp.com (usphx01srsp001v.us-phx01.nxp.com [134.27.49.11]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id CF3C62014B5; Thu, 25 Aug 2022 00:37:09 +0200 (CEST) Received: from right.am.freescale.net (right.am.freescale.net [10.81.116.134]) by usphx01srsp001v.us-phx01.nxp.com (Postfix) with ESMTP id 76E9D4060A; Wed, 24 Aug 2022 15:37:08 -0700 (MST) From: Li Yang To: shawnguo@kernel.org, devicetree@vger.kernel.org Cc: robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Hou Zhiqiang , Li Yang Subject: [PATCH 04/11] arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes Date: Wed, 24 Aug 2022 17:36:55 -0500 Message-Id: <20220824223700.32442-5-leoyang.li@nxp.com> X-Mailer: git-send-email 2.25.1.377.g2d2118b In-Reply-To: <20220824223700.32442-1-leoyang.li@nxp.com> References: <20220824223700.32442-1-leoyang.li@nxp.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Hou Zhiqiang The LS1043A PCIe controller has some control registers in SCFG block, so add the SCFG phandle for each PCIe controller node. Signed-off-by: Hou Zhiqiang Signed-off-by: Li Yang --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 242fe8bfab17..6b2bfb5c6f32 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -901,6 +901,7 @@ pcie1: pcie@3400000 { <0000 0 0 2 &gic 0 111 0x4>, <0000 0 0 3 &gic 0 112 0x4>, <0000 0 0 4 &gic 0 113 0x4>; + fsl,pcie-scfg = <&scfg 0>; status = "disabled"; }; @@ -927,6 +928,7 @@ pcie2: pcie@3500000 { <0000 0 0 2 &gic 0 121 0x4>, <0000 0 0 3 &gic 0 122 0x4>, <0000 0 0 4 &gic 0 123 0x4>; + fsl,pcie-scfg = <&scfg 1>; status = "disabled"; }; @@ -953,6 +955,7 @@ pcie3: pcie@3600000 { <0000 0 0 2 &gic 0 155 0x4>, <0000 0 0 3 &gic 0 156 0x4>, <0000 0 0 4 &gic 0 157 0x4>; + fsl,pcie-scfg = <&scfg 2>; status = "disabled"; }; -- 2.37.1