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From: Li Yang <leoyang.li@nxp.com>
To: shawnguo@kernel.org, devicetree@vger.kernel.org
Cc: robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Hou Zhiqiang <Zhiqiang.Hou@nxp.com>,
	Li Yang <leoyang.li@nxp.com>
Subject: [PATCH 3/9] arm64: dts: ls1046a: Add big-endian property for PCIe nodes
Date: Wed, 24 Aug 2022 18:11:54 -0500	[thread overview]
Message-ID: <20220824231200.494-4-leoyang.li@nxp.com> (raw)
In-Reply-To: <20220824231200.494-1-leoyang.li@nxp.com>

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Add the big-endian property for LS1046A PCIe nodes for accessing PEX_LUT
and PF register block.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index fce3c6401653..f8e8c1415c02 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -805,6 +805,7 @@ pcie1: pcie@3400000 {
 					<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			big-endian;
 			status = "disabled";
 		};
 
@@ -817,6 +818,7 @@ pcie_ep1: pcie_ep@3400000 {
 			interrupt-names = "pme";
 			num-ib-windows = <6>;
 			num-ob-windows = <8>;
+			big-endian;
 			status = "disabled";
 		};
 
@@ -843,6 +845,7 @@ pcie2: pcie@3500000 {
 					<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+			big-endian;
 			status = "disabled";
 		};
 
@@ -855,6 +858,7 @@ pcie_ep2: pcie_ep@3500000 {
 			interrupt-names = "pme";
 			num-ib-windows = <6>;
 			num-ob-windows = <8>;
+			big-endian;
 			status = "disabled";
 		};
 
@@ -881,6 +885,7 @@ pcie3: pcie@3600000 {
 					<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+			big-endian;
 			status = "disabled";
 		};
 
@@ -893,6 +898,7 @@ pcie_ep3: pcie_ep@3600000 {
 			interrupt-names = "pme";
 			num-ib-windows = <6>;
 			num-ob-windows = <8>;
+			big-endian;
 			status = "disabled";
 		};
 
-- 
2.37.1


  parent reply	other threads:[~2022-08-24 23:12 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-24 23:11 [PATCH 0/9] accumulated dts updates for ls1046a Li Yang
2022-08-24 23:11 ` [PATCH 1/9] arm64: dts: ls1046a: Enable usb3-lpm-capable for usb3 node Li Yang
2022-08-24 23:11 ` [PATCH 2/9] arm64: dts: ls1046a: Add the PME interrupt to PCIe EP nodes Li Yang
2022-09-05  1:10   ` Shawn Guo
2022-08-24 23:11 ` Li Yang [this message]
2022-08-24 23:11 ` [PATCH 4/9] arm64: dts: ls1046a: add missing dma ranges property Li Yang
2022-08-24 23:11 ` [PATCH 5/9] arm64: dts: ls1046a: make dma-coherent global to the SoC Li Yang
2022-08-24 23:11 ` [PATCH 6/9] arm64: dts: ls1046a: use a pseudo-bus to constrain usb and sata dma size Li Yang
2022-08-24 23:11 ` [PATCH 7/9] arm64: dts: ls1046a: add gpios based i2c recovery information Li Yang
2022-09-05  1:12   ` Shawn Guo
2022-08-24 23:11 ` [PATCH 8/9] arm64: dts: ls1046a-qds: add mmio based mdio-mux support Li Yang
2022-09-05  1:17   ` Shawn Guo
2022-08-24 23:12 ` [PATCH 9/9] arm64: dts: ls1046a-qds: Modify the qspi flash frequency Li Yang

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