From: Li Yang <leoyang.li@nxp.com>
To: shawnguo@kernel.org, devicetree@vger.kernel.org
Cc: robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Laurentiu Tudor <laurentiu.tudor@nxp.com>,
Robin Murphy <robin.murphy@arm.com>, Li Yang <leoyang.li@nxp.com>
Subject: [PATCH 6/9] arm64: dts: ls1046a: use a pseudo-bus to constrain usb and sata dma size
Date: Wed, 24 Aug 2022 18:11:57 -0500 [thread overview]
Message-ID: <20220824231200.494-7-leoyang.li@nxp.com> (raw)
In-Reply-To: <20220824231200.494-1-leoyang.li@nxp.com>
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Wrap the usb and sata controllers in an intermediate simple-bus and use
it to constrain the dma address size of these usb controllers to the 40
bits that they generate toward the interconnect. This is required
because the SoC uses 48 bits address sizes and this mismatch would lead
to smmu context faults because the usb generates 40-bit addresses while
the smmu page tables are populated with 48-bit wide addresses.
Suggested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 90 ++++++++++---------
1 file changed, 49 insertions(+), 41 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 10b6c41570cc..c7c6c82626fd 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -711,47 +711,55 @@ QORIQ_CLK_PLL_DIV(2)>,
QORIQ_CLK_PLL_DIV(2)>;
};
- usb0: usb@2f00000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x2f00000 0x0 0x10000>;
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- usb3-lpm-capable;
- };
-
- usb1: usb@3000000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x3000000 0x0 0x10000>;
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- usb3-lpm-capable;
- };
-
- usb2: usb@3100000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x3100000 0x0 0x10000>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,dis_rxdet_inp3_quirk;
- snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- usb3-lpm-capable;
- };
-
- sata: sata@3200000 {
- compatible = "fsl,ls1046a-ahci";
- reg = <0x0 0x3200000 0x0 0x10000>,
- <0x0 0x20140520 0x0 0x4>;
- reg-names = "ahci", "sata-ecc";
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
- QORIQ_CLK_PLL_DIV(2)>;
+ aux_bus: aux_bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
+
+ usb0: usb@2f00000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x2f00000 0x0 0x10000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
+ };
+
+ usb1: usb@3000000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3000000 0x0 0x10000>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
+ };
+
+ usb2: usb@3100000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb3-lpm-capable;
+ };
+
+ sata: sata@3200000 {
+ compatible = "fsl,ls1046a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>,
+ <0x0 0x20140520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ };
};
msi1: msi-controller@1580000 {
--
2.37.1
next prev parent reply other threads:[~2022-08-24 23:12 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-24 23:11 [PATCH 0/9] accumulated dts updates for ls1046a Li Yang
2022-08-24 23:11 ` [PATCH 1/9] arm64: dts: ls1046a: Enable usb3-lpm-capable for usb3 node Li Yang
2022-08-24 23:11 ` [PATCH 2/9] arm64: dts: ls1046a: Add the PME interrupt to PCIe EP nodes Li Yang
2022-09-05 1:10 ` Shawn Guo
2022-08-24 23:11 ` [PATCH 3/9] arm64: dts: ls1046a: Add big-endian property for PCIe nodes Li Yang
2022-08-24 23:11 ` [PATCH 4/9] arm64: dts: ls1046a: add missing dma ranges property Li Yang
2022-08-24 23:11 ` [PATCH 5/9] arm64: dts: ls1046a: make dma-coherent global to the SoC Li Yang
2022-08-24 23:11 ` Li Yang [this message]
2022-08-24 23:11 ` [PATCH 7/9] arm64: dts: ls1046a: add gpios based i2c recovery information Li Yang
2022-09-05 1:12 ` Shawn Guo
2022-08-24 23:11 ` [PATCH 8/9] arm64: dts: ls1046a-qds: add mmio based mdio-mux support Li Yang
2022-09-05 1:17 ` Shawn Guo
2022-08-24 23:12 ` [PATCH 9/9] arm64: dts: ls1046a-qds: Modify the qspi flash frequency Li Yang
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