From: Daniel Mack <daniel@zonque.org>
To: mturquette@baylibre.com, sboyd@kernel.org
Cc: linux-clk@vger.kernel.org, robh+dt@kernel.org,
devicetree@vger.kernel.org, kuninori.morimoto.gx@renesas.com,
Daniel Mack <daniel@zonque.org>
Subject: [PATCH v2 2/2] clk: cs2000-cp: make PLL lock timeout configurable
Date: Fri, 26 Aug 2022 11:11:22 +0200 [thread overview]
Message-ID: <20220826091122.2344503-2-daniel@zonque.org> (raw)
In-Reply-To: <20220826091122.2344503-1-daniel@zonque.org>
The driver currently does 256 iterations of reads from the DEVICE_CTRL
register to wait for the PLL_LOCK bit to clear, and sleeps one
microsecond after each attempt.
This isn't ideal because
a) the total time this allows for the device to settle depends on the I2C
bus speed, and
b) the device might need more time, depending on the application.
This patch allows users to configure this timeout through a new device-tree
property "cirrus,pll-lock-timeout-ms".
In order to not break existing applications, a default value of 100 ms is
assumed: For each read cycle, 8 bits are sent for the register address, and
8 bits are read with the values. 16 bits take about 160 us on a 100 kHz bus
and 40 us on a 400 kHz bus. Hence 256 iterations would take a maximum of
around 44 ms. Round up and double that value to be on the safe side.
Signed-off-by: Daniel Mack <daniel@zonque.org>
---
drivers/clk/clk-cs2000-cp.c | 25 +++++++++++++------------
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c
index aa5c72bab83e..2b33617727c2 100644
--- a/drivers/clk/clk-cs2000-cp.c
+++ b/drivers/clk/clk-cs2000-cp.c
@@ -110,6 +110,8 @@ struct cs2000_priv {
bool lf_ratio;
bool clk_skip;
+ unsigned int pll_lock_timeout_ms;
+
/* suspend/resume */
unsigned long saved_rate;
unsigned long saved_parent_rate;
@@ -171,21 +173,16 @@ static int cs2000_ref_clk_bound_rate(struct cs2000_priv *priv,
static int cs2000_wait_pll_lock(struct cs2000_priv *priv)
{
struct device *dev = priv_to_dev(priv);
- unsigned int i, val;
+ unsigned int val;
int ret;
- for (i = 0; i < 256; i++) {
- ret = regmap_read(priv->regmap, DEVICE_CTRL, &val);
- if (ret < 0)
- return ret;
- if (!(val & PLL_UNLOCK))
- return 0;
- udelay(1);
- }
-
- dev_err(dev, "pll lock failed\n");
+ ret = regmap_read_poll_timeout(priv->regmap, DEVICE_CTRL, val,
+ !(val & PLL_UNLOCK), USEC_PER_MSEC,
+ priv->pll_lock_timeout_ms * USEC_PER_MSEC);
+ if (ret < 0)
+ dev_err(dev, "pll lock failed\n");
- return -ETIMEDOUT;
+ return ret;
}
static int cs2000_clk_out_enable(struct cs2000_priv *priv, bool enable)
@@ -481,6 +478,10 @@ static int cs2000_clk_register(struct cs2000_priv *priv)
if (ret < 0)
return ret;
+ priv->pll_lock_timeout_ms = 100;
+ of_property_read_u32(np, "cirrus,pll-lock-timeout-ms",
+ &priv->pll_lock_timeout_ms);
+
priv->clk_skip = of_property_read_bool(np, "cirrus,clock-skip");
ref_clk_rate = clk_get_rate(priv->ref_clk);
--
2.37.2
next prev parent reply other threads:[~2022-08-26 9:12 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-26 9:11 [PATCH v2 1/2] dt-bindings: clock: cs2000-cp: Document cirrus,pll-lock-timeout-ms Daniel Mack
2022-08-26 9:11 ` Daniel Mack [this message]
2022-08-30 1:49 ` [PATCH v2 2/2] clk: cs2000-cp: make PLL lock timeout configurable Stephen Boyd
2022-08-30 20:25 ` Rob Herring
2022-08-31 13:25 ` Daniel Mack
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