From: Conor Dooley <conor.dooley@microchip.com>
To: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor.dooley@microchip.com>,
Daire McNamara <daire.mcnamara@microchip.com>,
Shravan Chippa <shravan.chippa@microchip.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Cyril Jean <Cyril.Jean@microchip.com>,
Lewis Hanly <lewis.hanly@microchip.com>,
Vattipalli Praveen <praveen.kumar@microchip.com>,
Wolfgang Grandegger <wg@aries-embedded.de>,
<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH 7/9] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses
Date: Fri, 26 Aug 2022 15:28:05 +0100 [thread overview]
Message-ID: <20220826142806.3658434-8-conor.dooley@microchip.com> (raw)
In-Reply-To: <20220826142806.3658434-1-conor.dooley@microchip.com>
When users try to add onto the reference design, they find that the
current addresses that peripherals connected to Fabric InterConnect
(FIC) 3 use are restrictive. For the v2022.09 reference design, the
peripherals have been shifted down, leaving more contiguous address
space for their custom IP/peripherals.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index 32d51c4a5b0c..98f04be0dc6b 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -6,18 +6,18 @@ / {
compatible = "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpfs-icicle-kit",
"microchip,mpfs";
- core_pwm0: pwm@41000000 {
+ core_pwm0: pwm@40000000 {
compatible = "microchip,corepwm-rtl-v4";
- reg = <0x0 0x41000000 0x0 0xF0>;
+ reg = <0x0 0x40000000 0x0 0xF0>;
microchip,sync-update-mask = /bits/ 32 <0>;
#pwm-cells = <2>;
clocks = <&fabric_clk3>;
status = "disabled";
};
- i2c2: i2c@44000000 {
+ i2c2: i2c@40000200 {
compatible = "microchip,corei2c-rtl-v7";
- reg = <0x0 0x44000000 0x0 0x1000>;
+ reg = <0x0 0x40000200 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&fabric_clk3>;
--
2.36.1
next prev parent reply other threads:[~2022-08-26 14:29 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-26 14:27 [PATCH 0/9] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
2022-08-26 14:27 ` [PATCH 1/9] dt-bindings: riscv: microchip: document icicle reference design Conor Dooley
2022-08-27 9:21 ` Krzysztof Kozlowski
2022-08-26 14:28 ` [PATCH 2/9] dt-bindings: riscv: microchip: document the aries m100pfsevp Conor Dooley
2022-08-27 9:22 ` Krzysztof Kozlowski
2022-08-26 14:28 ` [PATCH 3/9] dt-bindings: riscv: microchip: document the sev kit Conor Dooley
2022-08-27 9:23 ` Krzysztof Kozlowski
2022-08-26 14:28 ` [PATCH 4/9] riscv: dts: microchip: add pci dma ranges for the icicle kit Conor Dooley
2022-08-26 14:28 ` [PATCH 5/9] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi Conor Dooley
2022-08-26 14:28 ` [PATCH 6/9] riscv: dts: microchip: icicle: update pci address properties Conor Dooley
2022-08-26 14:28 ` Conor Dooley [this message]
2022-08-26 14:28 ` [PATCH 8/9] riscv: dts: microchip: add sevkit device tree Conor Dooley
2022-08-26 14:28 ` [PATCH 9/9] riscv: dts: microchip: add a devicetree for aries' m100pfsevp Conor Dooley
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