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[68.147.0.187]) by smtp.gmail.com with ESMTPSA id x9-20020a170902a38900b0016f154c8910sm5644434pla.204.2022.08.29.10.46.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 10:46:42 -0700 (PDT) Date: Mon, 29 Aug 2022 11:46:38 -0600 From: Mathieu Poirier To: Tinghan Shen Cc: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Lee Jones , Benson Leung , Guenter Roeck , Sebastian Reichel , Daisuke Nojiri , Kees Cook , "Gustavo A. R. Silva" , Prashant Malani , Enric Balletbo i Serra , linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev, Project_Global_Chrome_Upstream_Group@mediatek.com, weishunc@google.com Subject: Re: [PATCH v2 3/9] remoteproc: mediatek: Add SCP core 1 register definitions Message-ID: <20220829174638.GB2264818@p14s> References: <20220608083553.8697-1-tinghan.shen@mediatek.com> <20220608083553.8697-4-tinghan.shen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220608083553.8697-4-tinghan.shen@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Jun 08, 2022 at 04:35:47PM +0800, Tinghan Shen wrote: > Add MT8195 SCP core 1 related register definitions. > > Signed-off-by: Tinghan Shen > --- > drivers/remoteproc/mtk_common.h | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h > index 73e8adf00de3..5582f4207fbf 100644 > --- a/drivers/remoteproc/mtk_common.h > +++ b/drivers/remoteproc/mtk_common.h > @@ -47,6 +47,7 @@ > #define MT8192_SCP2SPM_IPC_CLR 0x4094 > #define MT8192_GIPC_IN_SET 0x4098 > #define MT8192_HOST_IPC_INT_BIT BIT(0) > +#define MT8195_CORE1_HOST_IPC_INT_BIT BIT(4) > > #define MT8192_CORE0_SW_RSTN_CLR 0x10000 > #define MT8192_CORE0_SW_RSTN_SET 0x10004 > @@ -60,6 +61,26 @@ > > #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) > > +#define MT8195_CPU1_SRAM_PD 0x1084 > +#define MT8195_SSHUB2APMCU_IPC_SET 0x4088 > +#define MT8195_SSHUB2APMCU_IPC_CLR 0x408C > +#define MT8195_CORE1_SW_RSTN_CLR 0x20000 > +#define MT8195_CORE1_SW_RSTN_SET 0x20004 > +#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 > +#define MT8195_CORE1_WDT_IRQ 0x20030 > +#define MT8195_CORE1_WDT_CFG 0x20034 > + > +#define MT8195_SEC_CTRL 0x85000 > +#define MT8195_CORE_OFFSET_ENABLE_D BIT(13) > +#define MT8195_CORE_OFFSET_ENABLE_I BIT(12) > +#define MT8195_L2TCM_OFFSET_RANGE_0_LOW 0x850b0 > +#define MT8195_L2TCM_OFFSET_RANGE_0_HIGH 0x850b4 > +#define MT8195_L2TCM_OFFSET 0x850d0 > +#define SCP_SRAM_REMAP_LOW 0 > +#define SCP_SRAM_REMAP_HIGH 1 > +#define SCP_SRAM_REMAP_OFFSET 2 > +#define SCP_SRAM_REMAP_SIZE 3 > + > #define SCP_FW_VER_LEN 32 > #define SCP_SHARE_BUFFER_SIZE 288 Reviewed-by: Mathieu Poirier > > -- > 2.18.0 >