[PATCH 0/2] MT8195: Add reset for T-PHY (usb/pcie)

[PATCH 0/2] MT8195: Add reset for T-PHY (usb/pcie)

[AngeloGioacchino Del Regno]

Add the resets for TPHY Port 1 which, depending on the board layout,
is used either as USB or PCIe PHY.

This is required on MT8195 Tomato Chromebooks for correct initialization
of the secondary PCI-Express controller, where we have a MT7621 PCIe
WiFi chip.

For reference, the PCIe1 controller devicetree node resets will look
like this:

pcie@112f8000 {
	... blurb ...

	resets = <&infracfg_ao MT8195_INFRA_RST2_USBSIF_P1_SWRST>,
		 <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>;
	reset-names = "phy", "mac";

	... blurb ...
};

This series depends on an earlier one where I introduce the MAC
resets for both PCIe (p0, p1) controllers [1]

[1]: https://patchwork.kernel.org/project/linux-mediatek/list/?series=654980

AngeloGioacchino Del Regno (2):
  dt-bindings: reset: mt8195: Add resets for USB/PCIe t-phy port 1
  clk: mediatek: mt8195: Add reset idx for USB/PCIe T-PHY

 drivers/clk/mediatek/clk-mt8195-infra_ao.c | 1 +
 include/dt-bindings/reset/mt8195-resets.h  | 1 +
 2 files changed, 2 insertions(+)

-- 
2.35.1

[PATCH 1/2] dt-bindings: reset: mt8195: Add resets for USB/PCIe t-phy port 1

[AngeloGioacchino Del Regno]

Add the reset index for USBSIF P1 (T-PHY port 1), used as either USB
or PCI-Express PHY reset.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 include/dt-bindings/reset/mt8195-resets.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index 5471468c43b7..e61660438d61 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -33,6 +33,7 @@
 #define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST 2
 #define MT8195_INFRA_RST2_PCIE_P0_SWRST        3
 #define MT8195_INFRA_RST2_PCIE_P1_SWRST        4
+#define MT8195_INFRA_RST2_USBSIF_P1_SWRST      5
 
 /* VDOSYS1 */
 #define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB2                     0
-- 
2.35.1

Re: [PATCH 1/2] dt-bindings: reset: mt8195: Add resets for USB/PCIe t-phy port 1

[Rob Herring]

On Wed, 20 Jul 2022 12:28:16 +0200, AngeloGioacchino Del Regno wrote:
> Add the reset index for USBSIF P1 (T-PHY port 1), used as either USB
> or PCI-Express PHY reset.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  include/dt-bindings/reset/mt8195-resets.h | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 1/2] dt-bindings: reset: mt8195: Add resets for USB/PCIe t-phy port 1

[Stephen Boyd]

Quoting AngeloGioacchino Del Regno (2022-07-20 03:28:16)
> Add the reset index for USBSIF P1 (T-PHY port 1), used as either USB
> or PCI-Express PHY reset.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---

Applied to clk-next

[PATCH 2/2] clk: mediatek: mt8195: Add reset idx for USB/PCIe T-PHY

[AngeloGioacchino Del Regno]

Add the reset idx for the t-phy port 1, used as either USB or
PCI-Express (secondary controller) PHY, depending on board-specific
configuration/layout.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-mt8195-infra_ao.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c
index 75b54ec9c46c..fcd410461d3b 100644
--- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c
+++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c
@@ -200,6 +200,7 @@ static u16 infra_ao_rst_ofs[] = {
 
 static u16 infra_ao_idx_map[] = {
 	[MT8195_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
+	[MT8195_INFRA_RST2_USBSIF_P1_SWRST] = 2 * RST_NR_PER_BANK + 18,
 	[MT8195_INFRA_RST2_PCIE_P0_SWRST] = 2 * RST_NR_PER_BANK + 26,
 	[MT8195_INFRA_RST2_PCIE_P1_SWRST] = 2 * RST_NR_PER_BANK + 27,
 	[MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
-- 
2.35.1

Re: [PATCH 2/2] clk: mediatek: mt8195: Add reset idx for USB/PCIe T-PHY

[Stephen Boyd]

Quoting AngeloGioacchino Del Regno (2022-07-20 03:28:17)
> Add the reset idx for the t-phy port 1, used as either USB or
> PCI-Express (secondary controller) PHY, depending on board-specific
> configuration/layout.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---

Applied to clk-next