From: Shawn Guo <shawnguo@kernel.org>
To: Li Yang <leoyang.li@nxp.com>
Cc: devicetree@vger.kernel.org, robh+dt@kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Laurentiu Tudor <laurentiu.tudor@nxp.com>,
Robin Murphy <robin.murphy@arm.com>
Subject: Re: [PATCH 09/11] arm64: dts: ls1043a: use a pseudo-bus to constrain usb and sata dma size
Date: Mon, 5 Sep 2022 09:09:21 +0800 [thread overview]
Message-ID: <20220905010921.GQ1728671@dragon> (raw)
In-Reply-To: <20220824223700.32442-10-leoyang.li@nxp.com>
On Wed, Aug 24, 2022 at 05:37:00PM -0500, Li Yang wrote:
> From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>
> Wrap the usb and sata controllers in an intermediate simple-bus and use
> it to constrain the dma address size of these usb controllers to the 40
> bits that they generate toward the interconnect. This is required
> because the SoC uses 48 bits address sizes and this mismatch would lead
> to smmu context faults because the usb generates 40-bit addresses while
> the smmu page tables are populated with 48-bit wide addresses.
>
> Suggested-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> ---
> .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 92 ++++++++++---------
> 1 file changed, 50 insertions(+), 42 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> index 20888aceb5f4..1942ab84ab1c 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> @@ -815,51 +815,59 @@ QORIQ_CLK_PLL_DIV(1)>,
> QORIQ_CLK_PLL_DIV(1)>;
> };
>
> - usb0: usb@2f00000 {
> - compatible = "snps,dwc3";
> - reg = <0x0 0x2f00000 0x0 0x10000>;
> - interrupts = <0 60 0x4>;
> - dr_mode = "host";
> - snps,quirk-frame-length-adjustment = <0x20>;
> - snps,dis_rxdet_inp3_quirk;
> - usb3-lpm-capable;
> - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
> - status = "disabled";
> - };
> + aux_bus: aux_bus {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
> +
> + usb0: usb@2f00000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0x2f00000 0x0 0x10000>;
> + interrupts = <0 60 0x4>;
While at it, use define for polarity cell?
Shawn
> + dr_mode = "host";
> + snps,quirk-frame-length-adjustment = <0x20>;
> + snps,dis_rxdet_inp3_quirk;
> + usb3-lpm-capable;
> + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
> + status = "disabled";
> + };
>
> - usb1: usb@3000000 {
> - compatible = "snps,dwc3";
> - reg = <0x0 0x3000000 0x0 0x10000>;
> - interrupts = <0 61 0x4>;
> - dr_mode = "host";
> - snps,quirk-frame-length-adjustment = <0x20>;
> - snps,dis_rxdet_inp3_quirk;
> - usb3-lpm-capable;
> - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
> - status = "disabled";
> - };
> + usb1: usb@3000000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0x3000000 0x0 0x10000>;
> + interrupts = <0 61 0x4>;
> + dr_mode = "host";
> + snps,quirk-frame-length-adjustment = <0x20>;
> + snps,dis_rxdet_inp3_quirk;
> + usb3-lpm-capable;
> + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
> + status = "disabled";
> + };
>
> - usb2: usb@3100000 {
> - compatible = "snps,dwc3";
> - reg = <0x0 0x3100000 0x0 0x10000>;
> - interrupts = <0 63 0x4>;
> - dr_mode = "host";
> - snps,quirk-frame-length-adjustment = <0x20>;
> - snps,dis_rxdet_inp3_quirk;
> - usb3-lpm-capable;
> - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
> - status = "disabled";
> - };
> + usb2: usb@3100000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0x3100000 0x0 0x10000>;
> + interrupts = <0 63 0x4>;
> + dr_mode = "host";
> + snps,quirk-frame-length-adjustment = <0x20>;
> + snps,dis_rxdet_inp3_quirk;
> + usb3-lpm-capable;
> + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
> + status = "disabled";
> + };
>
> - sata: sata@3200000 {
> - compatible = "fsl,ls1043a-ahci";
> - reg = <0x0 0x3200000 0x0 0x10000>,
> - <0x0 0x20140520 0x0 0x4>;
> - reg-names = "ahci", "sata-ecc";
> - interrupts = <0 69 0x4>;
> - clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> - QORIQ_CLK_PLL_DIV(1)>;
> - dma-coherent;
> + sata: sata@3200000 {
> + compatible = "fsl,ls1043a-ahci";
> + reg = <0x0 0x3200000 0x0 0x10000>,
> + <0x0 0x20140520 0x0 0x4>;
> + reg-names = "ahci", "sata-ecc";
> + interrupts = <0 69 0x4>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(1)>;
> + dma-coherent;
> + };
> };
>
> msi1: msi-controller1@1571000 {
> --
> 2.37.1
>
prev parent reply other threads:[~2022-09-05 1:09 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-24 22:36 [PATCH 00/11] accumulated dts updates for ls1043a Li Yang
2022-08-24 22:36 ` [PATCH 01/11] arm64: dts: ls1043a: fix the wrong size of dcfg space Li Yang
2022-08-24 22:36 ` [PATCH 02/11] arm64: dts: ls1043a: Enable usb3-lpm-capable for usb3 node Li Yang
2022-08-24 22:36 ` [PATCH 03/11] arm64: dts: ls1043a: use pcie aer/pme interrupts Li Yang
2022-09-05 1:05 ` Shawn Guo
2022-08-24 22:36 ` [PATCH 04/11] arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes Li Yang
2022-08-24 22:36 ` [PATCH 05/11] arm64: dts: ls1043a: Add big-endian property " Li Yang
2022-08-24 22:36 ` [PATCH 06/11] arm64: dts: ls1043a: add missing dma ranges property Li Yang
2022-08-24 22:36 ` [PATCH 07/11] arm64: dts: ls1043a: make dma-coherent global to the SoC Li Yang
2022-08-24 22:36 ` [PATCH 08/11] arm64: dts: ls1043a: add gpio based i2c recovery information Li Yang
2022-09-05 1:06 ` Shawn Guo
2022-08-24 22:37 ` [PATCH 09/11] arm64: dts: ls1043a: use a pseudo-bus to constrain usb and sata dma size Li Yang
2022-09-05 1:09 ` Shawn Guo [this message]
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