From: Shawn Guo <shawnguo@kernel.org>
To: Li Yang <leoyang.li@nxp.com>
Cc: devicetree@vger.kernel.org, robh+dt@kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: Re: [PATCH 2/9] arm64: dts: ls1046a: Add the PME interrupt to PCIe EP nodes
Date: Mon, 5 Sep 2022 09:10:59 +0800 [thread overview]
Message-ID: <20220905011059.GR1728671@dragon> (raw)
In-Reply-To: <20220824231200.494-3-leoyang.li@nxp.com>
On Wed, Aug 24, 2022 at 06:11:53PM -0500, Li Yang wrote:
> From: Xiaowei Bao <xiaowei.bao@nxp.com>
>
> Add the PME interrupt property to the PCIe EP nodes.
>
> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> index ddae3cb0a977..fce3c6401653 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> @@ -813,6 +813,8 @@ pcie_ep1: pcie_ep@3400000 {
> reg = <0x00 0x03400000 0x0 0x00100000>,
> <0x40 0x00000000 0x8 0x00000000>;
> reg-names = "regs", "addr_space";
> + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
The comment seems unnecessary, considering we have the interrupt-names
below?
Shawn
> + interrupt-names = "pme";
> num-ib-windows = <6>;
> num-ob-windows = <8>;
> status = "disabled";
> @@ -849,6 +851,8 @@ pcie_ep2: pcie_ep@3500000 {
> reg = <0x00 0x03500000 0x0 0x00100000>,
> <0x48 0x00000000 0x8 0x00000000>;
> reg-names = "regs", "addr_space";
> + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
> + interrupt-names = "pme";
> num-ib-windows = <6>;
> num-ob-windows = <8>;
> status = "disabled";
> @@ -885,6 +889,8 @@ pcie_ep3: pcie_ep@3600000 {
> reg = <0x00 0x03600000 0x0 0x00100000>,
> <0x50 0x00000000 0x8 0x00000000>;
> reg-names = "regs", "addr_space";
> + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
> + interrupt-names = "pme";
> num-ib-windows = <6>;
> num-ob-windows = <8>;
> status = "disabled";
> --
> 2.37.1
>
next prev parent reply other threads:[~2022-09-05 1:11 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-24 23:11 [PATCH 0/9] accumulated dts updates for ls1046a Li Yang
2022-08-24 23:11 ` [PATCH 1/9] arm64: dts: ls1046a: Enable usb3-lpm-capable for usb3 node Li Yang
2022-08-24 23:11 ` [PATCH 2/9] arm64: dts: ls1046a: Add the PME interrupt to PCIe EP nodes Li Yang
2022-09-05 1:10 ` Shawn Guo [this message]
2022-08-24 23:11 ` [PATCH 3/9] arm64: dts: ls1046a: Add big-endian property for PCIe nodes Li Yang
2022-08-24 23:11 ` [PATCH 4/9] arm64: dts: ls1046a: add missing dma ranges property Li Yang
2022-08-24 23:11 ` [PATCH 5/9] arm64: dts: ls1046a: make dma-coherent global to the SoC Li Yang
2022-08-24 23:11 ` [PATCH 6/9] arm64: dts: ls1046a: use a pseudo-bus to constrain usb and sata dma size Li Yang
2022-08-24 23:11 ` [PATCH 7/9] arm64: dts: ls1046a: add gpios based i2c recovery information Li Yang
2022-09-05 1:12 ` Shawn Guo
2022-08-24 23:11 ` [PATCH 8/9] arm64: dts: ls1046a-qds: add mmio based mdio-mux support Li Yang
2022-09-05 1:17 ` Shawn Guo
2022-08-24 23:12 ` [PATCH 9/9] arm64: dts: ls1046a-qds: Modify the qspi flash frequency Li Yang
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