From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7EAFCECAAD5 for ; Mon, 5 Sep 2022 02:22:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231814AbiIECWh (ORCPT ); Sun, 4 Sep 2022 22:22:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231830AbiIECWh (ORCPT ); Sun, 4 Sep 2022 22:22:37 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F2DC2716E for ; Sun, 4 Sep 2022 19:22:36 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9FEC461049 for ; Mon, 5 Sep 2022 02:22:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 61409C433D6; Mon, 5 Sep 2022 02:22:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1662344555; bh=916uXypaAnZ9d2zo9QefAmHgvekVDX7XVcreYrQhrqc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=r8FdPtVN0Xuw1fs7oWy96arw4QRiVRZtu+bIuqrcFSaP/udNuyBgdTwf7wCQZzLea d2hplsPM6sYrfmOUoM4SUPhnVlsIv9Mr+oHwpiXNegippPGj3p4rjvmsKWImYli2y3 G9ykngcxDqwVelkgSEdz4/I+NY1XezK5McDvNupq7SknA1YCMcr6AGRduVgN3bM58v ZGVT6mcaI1LLUjhji8Bv2c5wsEMxst5QLoA/lMUj0U/WqZrITKGSRL8LoyF3dN+E/j AuMnTNLi+SsaZPOydnQHMMmwhnmdWFSHRBmc3S7GIMH7hcb1Y6ms0gzv0TBi44dpy5 VYCL2e20LJWpA== Date: Mon, 5 Sep 2022 10:22:28 +0800 From: Shawn Guo To: Alexander Stein Cc: Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tim Harvey , Jun Li Subject: Re: [PATCH v2 1/1] arm64: dts: tqma8mpql: add USB DR support Message-ID: <20220905022228.GB1728671@dragon> References: <20220831074606.1677052-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220831074606.1677052-1-alexander.stein@ew.tq-group.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Aug 31, 2022 at 09:46:06AM +0200, Alexander Stein wrote: > Add support for USB DR on USB1 interface. Host/Device detection is done > using the usb-role-switch connector. > > Signed-off-by: Alexander Stein > --- > Changes in v2: > * Split from previous series > * For now enable USB OTG only > > .../freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 40 +++++++++++++++++++ > 1 file changed, 40 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts > index d8ca52976170..b30d75b1fa47 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts > @@ -459,6 +459,37 @@ &usdhc2 { > status = "okay"; > }; > > +&usb3_phy0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usb0>; Should the pinctrl be in USB controller instead of PHY node? > + status = "okay"; > +}; > + > +&usb3_0 { > + fsl,over-current-active-low; > + status = "okay"; > +}; > + > +&usb_dwc3_0 { These nodes are not in alphabetic order. > + /* dual role is implemented, but not a full featured OTG */ > + hnp-disable; > + srp-disable; > + adp-disable; > + dr_mode = "otg"; > + usb-role-switch; > + role-switch-default-mode = "peripheral"; > + status = "okay"; > + > + connector { > + compatible = "gpio-usb-b-connector", "usb-b-connector"; > + type = "micro"; > + label = "X29"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usbcon0>; > + id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; > + }; > +}; > + > &iomuxc { > pinctrl_backlight: backlightgrp { > fsl,pins = ; > @@ -666,6 +697,15 @@ pinctrl_uart4: uart4grp { > ; > }; > > + pinctrl_usbcon0: usb0congrp { > + fsl,pins = ; > + }; > + > + pinctrl_usb0: usb0grp { pinctrl_usb0 should go before pinctrl_usbcon0? Shawn > + fsl,pins = , > + ; > + }; > + > pinctrl_usdhc2: usdhc2grp { > fsl,pins = , > , > -- > 2.25.1 >