[PATCH v3 7/7] ARM: dts: orion5x: Add PCIe node

["Pali Rohár" <pali@kernel.org>]

Define PCIe aperture for top level soc node handled by mbus driver and
define PCIe controller node with one PCIe Root Port.

Old Orion arch code maps first 16 MB of PCIe config space to physical
address 0xf0000000. But for full PCIe support it is needed to map whole
256 MB long PCIe config space.

There are probably no Orion boards with more than 2 GB of RAM, so 256 MB of
free physical address space must exist. Tests on Orion board proved that
there is free space in physical address range 0xd0000000-0xdfffffff.

So use this physical space for mapping whole 256 MB long PCIe config space.
In case there would be some issue with this range, particular Orion device
tree board file can change it to 16 MB size or move it to old location.

By default orion5x.dtsi include file would contains whole PCIe config space
for full PCIe support.

By default is PCIe node disabled, so this change in orion5x.dtsi has no
effect for any board until board dts file explicitly enable it. Each board
has to migrate its PCIe code from old arch specific to device tree based.

Signed-off-by: Pali Rohár <pali@kernel.org>
---
Changes in v3:
* New patch
---
 arch/arm/boot/dts/orion5x.dtsi | 51 ++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index 2d41f5c166ee..41954d96ebbf 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -18,6 +18,9 @@
 		#address-cells = <2>;
 		#size-cells = <1>;
 		controller = <&mbusc>;
+		pcie-cfg-aperture = <0xd0000000 0x10000000>; /* 256 MiB config space */
+		pcie-mem-aperture = <0xe0000000 0x08000000>; /* 128 MiB memory space */
+		pcie-io-aperture  = <0xf2000000 0x00100000>; /*   1 MiB I/O space */
 
 		devbus_bootcs: devbus-bootcs {
 			compatible = "marvell,orion-devbus";
@@ -226,6 +229,54 @@
 			};
 		};
 
+		pciec: pcie {
+			compatible = "marvell,orion5x-pcie";
+			status = "disabled";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			msi-parent = <&intc>;
+			bus-range = <0x00 0xff>;
+
+			ranges = <0x82000000 0x0    0x40000  MBUS_ID(0xf0, 0x01) 0x40000  0x0     0x2000>, /* Port 0.0 Internal registers */
+				 <0x82000000 0x0 0xf0000000  MBUS_ID(0x04, 0x79)     0x0  0x0 0x10000000>, /* Port 0.0 Config space registers */
+				 <0x82000000 0x1 0x00000000  MBUS_ID(0x04, 0x59)     0x0  0x1 0x00000000>, /* Port 0.0 Mem */
+				 <0x81000000 0x1 0x00000000  MBUS_ID(0x04, 0x51)     0x0  0x1 0x00000000>; /* Port 0.0 I/O */
+
+			pcie0: pcie@1,0 {
+				status = "disabled";
+				reg = <0x0800 0 0 0 0>;
+				device_type = "pci";
+				#address-cells = <3>;
+				#size-cells = <2>;
+
+				assigned-addresses =         <0x82000800 0x0    0x40000  0x0     0x2000>, /* Port 0.0 Internal registers */
+						             <0x82000800 0x0 0xf0000000  0x0 0x10000000>; /* Port 0.0 Config space registers */
+				ranges = <0x82000000 0x0 0x0  0x82000000 0x1 0x00000000  0x1 0x00000000>, /* Port 0.0 Mem */
+				         <0x81000000 0x0 0x0  0x81000000 0x1 0x00000000  0x1 0x00000000>; /* Port 0.0 I/O */
+				bus-range = <0x00 0xff>;
+
+				clocks = <&core_clk 0>;
+				marvell,pcie-port = <0>;
+				marvell,pcie-lane = <0>;
+
+				#interrupt-cells = <1>;
+				interrupt-names = "intx", "error";
+				interrupts = <11>, <10>;
+				interrupt-map-mask = <0 0 0 7>;
+				interrupt-map = <0 0 0 1 &pcie_intc 0>,
+						<0 0 0 2 &pcie_intc 1>,
+						<0 0 0 3 &pcie_intc 2>,
+						<0 0 0 4 &pcie_intc 3>;
+
+				pcie_intc: interrupt-controller {
+					interrupt-controller;
+					#interrupt-cells = <1>;
+				};
+			};
+		};
+
 		crypto_sram: sa-sram {
 			compatible = "mmio-sram";
 			reg = <MBUS_ID(0x09, 0x00) 0x0 0x800>;
-- 
2.20.1