From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@somainline.org>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Taniya Das <quic_tdas@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org
Subject: [PATCH v2 2/5] clk: qcom: gcc-msm8660: use ARRAY_SIZE instead of specifying num_parents
Date: Fri, 9 Sep 2022 13:51:33 +0300 [thread overview]
Message-ID: <20220909105136.3733919-3-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20220909105136.3733919-1-dmitry.baryshkov@linaro.org>
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-msm8660.c | 82 +++++++++++++++++-----------------
1 file changed, 41 insertions(+), 41 deletions(-)
diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c
index 94ea2d84d1b1..3c623dc4977b 100644
--- a/drivers/clk/qcom/gcc-msm8660.c
+++ b/drivers/clk/qcom/gcc-msm8660.c
@@ -123,7 +123,7 @@ static struct clk_rcg gsbi1_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -174,7 +174,7 @@ static struct clk_rcg gsbi2_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -225,7 +225,7 @@ static struct clk_rcg gsbi3_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi3_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -276,7 +276,7 @@ static struct clk_rcg gsbi4_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -327,7 +327,7 @@ static struct clk_rcg gsbi5_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -378,7 +378,7 @@ static struct clk_rcg gsbi6_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi6_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -429,7 +429,7 @@ static struct clk_rcg gsbi7_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi7_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -480,7 +480,7 @@ static struct clk_rcg gsbi8_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi8_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -529,7 +529,7 @@ static struct clk_rcg gsbi9_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi9_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -578,7 +578,7 @@ static struct clk_rcg gsbi10_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi10_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -627,7 +627,7 @@ static struct clk_rcg gsbi11_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi11_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -676,7 +676,7 @@ static struct clk_rcg gsbi12_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi12_uart_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -738,7 +738,7 @@ static struct clk_rcg gsbi1_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -787,7 +787,7 @@ static struct clk_rcg gsbi2_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -836,7 +836,7 @@ static struct clk_rcg gsbi3_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi3_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -885,7 +885,7 @@ static struct clk_rcg gsbi4_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -934,7 +934,7 @@ static struct clk_rcg gsbi5_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -983,7 +983,7 @@ static struct clk_rcg gsbi6_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi6_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1032,7 +1032,7 @@ static struct clk_rcg gsbi7_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi7_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1081,7 +1081,7 @@ static struct clk_rcg gsbi8_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi8_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1130,7 +1130,7 @@ static struct clk_rcg gsbi9_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi9_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1179,7 +1179,7 @@ static struct clk_rcg gsbi10_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi10_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1228,7 +1228,7 @@ static struct clk_rcg gsbi11_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi11_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1277,7 +1277,7 @@ static struct clk_rcg gsbi12_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi12_qup_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1339,7 +1339,7 @@ static struct clk_rcg gp0_src = {
.hw.init = &(struct clk_init_data){
.name = "gp0_src",
.parent_names = gcc_pxo_pll8_cxo,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1388,7 +1388,7 @@ static struct clk_rcg gp1_src = {
.hw.init = &(struct clk_init_data){
.name = "gp1_src",
.parent_names = gcc_pxo_pll8_cxo,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1437,7 +1437,7 @@ static struct clk_rcg gp2_src = {
.hw.init = &(struct clk_init_data){
.name = "gp2_src",
.parent_names = gcc_pxo_pll8_cxo,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1489,7 +1489,7 @@ static struct clk_rcg prng_src = {
.init = &(struct clk_init_data){
.name = "prng_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
},
@@ -1548,7 +1548,7 @@ static struct clk_rcg sdc1_src = {
.hw.init = &(struct clk_init_data){
.name = "sdc1_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -1596,7 +1596,7 @@ static struct clk_rcg sdc2_src = {
.hw.init = &(struct clk_init_data){
.name = "sdc2_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -1644,7 +1644,7 @@ static struct clk_rcg sdc3_src = {
.hw.init = &(struct clk_init_data){
.name = "sdc3_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -1692,7 +1692,7 @@ static struct clk_rcg sdc4_src = {
.hw.init = &(struct clk_init_data){
.name = "sdc4_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -1740,7 +1740,7 @@ static struct clk_rcg sdc5_src = {
.hw.init = &(struct clk_init_data){
.name = "sdc5_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -1793,7 +1793,7 @@ static struct clk_rcg tsif_ref_src = {
.hw.init = &(struct clk_init_data){
.name = "tsif_ref_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1847,7 +1847,7 @@ static struct clk_rcg usb_hs1_xcvr_src = {
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1896,7 +1896,7 @@ static struct clk_rcg usb_fs1_xcvr_fs_src = {
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_xcvr_fs_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1914,7 +1914,7 @@ static struct clk_branch usb_fs1_xcvr_fs_clk = {
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_xcvr_fs_clk",
.parent_names = usb_fs1_xcvr_fs_src_p,
- .num_parents = 1,
+ .num_parents = ARRAY_SIZE(usb_fs1_xcvr_fs_src_p),
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -1929,7 +1929,7 @@ static struct clk_branch usb_fs1_system_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.parent_names = usb_fs1_xcvr_fs_src_p,
- .num_parents = 1,
+ .num_parents = ARRAY_SIZE(usb_fs1_xcvr_fs_src_p),
.name = "usb_fs1_system_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1963,7 +1963,7 @@ static struct clk_rcg usb_fs2_xcvr_fs_src = {
.hw.init = &(struct clk_init_data){
.name = "usb_fs2_xcvr_fs_src",
.parent_names = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1981,7 +1981,7 @@ static struct clk_branch usb_fs2_xcvr_fs_clk = {
.hw.init = &(struct clk_init_data){
.name = "usb_fs2_xcvr_fs_clk",
.parent_names = usb_fs2_xcvr_fs_src_p,
- .num_parents = 1,
+ .num_parents = ARRAY_SIZE(usb_fs2_xcvr_fs_src_p),
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -1997,7 +1997,7 @@ static struct clk_branch usb_fs2_system_clk = {
.hw.init = &(struct clk_init_data){
.name = "usb_fs2_system_clk",
.parent_names = usb_fs2_xcvr_fs_src_p,
- .num_parents = 1,
+ .num_parents = ARRAY_SIZE(usb_fs2_xcvr_fs_src_p),
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
--
2.35.1
next prev parent reply other threads:[~2022-09-09 10:51 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-09 10:51 [PATCH v2 0/5] ARM: msm8660: change gcc to use parent_hws/data Dmitry Baryshkov
2022-09-09 10:51 ` [PATCH v2 1/5] dt-bindings: clock: qcom,gcc-msm8660: separate GCC bindings for MSM8660 Dmitry Baryshkov
2022-09-14 8:11 ` Linus Walleij
2022-09-09 10:51 ` Dmitry Baryshkov [this message]
2022-09-09 12:59 ` [PATCH v2 2/5] clk: qcom: gcc-msm8660: use ARRAY_SIZE instead of specifying num_parents Krzysztof Kozlowski
2022-09-14 8:14 ` Linus Walleij
2022-09-09 10:51 ` [PATCH v2 3/5] clk: qcom: gcc-msm8660: use parent_hws/_data instead of parent_names Dmitry Baryshkov
2022-09-14 8:18 ` Linus Walleij
2022-09-09 10:51 ` [PATCH v2 4/5] ARM: dts: qcom: msm8660: add pxo/cxo clocks to the GCC node Dmitry Baryshkov
2022-09-14 8:21 ` Linus Walleij
2022-09-09 10:51 ` [PATCH v2 5/5] ARM: dts: qcom-msm8660: fix node names for fixed clocks Dmitry Baryshkov
2022-09-09 13:00 ` Krzysztof Kozlowski
2022-09-14 8:23 ` Linus Walleij
2022-09-13 22:48 ` (subset) [PATCH v2 0/5] ARM: msm8660: change gcc to use parent_hws/data Bjorn Andersson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220909105136.3733919-3-dmitry.baryshkov@linaro.org \
--to=dmitry.baryshkov@linaro.org \
--cc=agross@kernel.org \
--cc=andersson@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=konrad.dybcio@somainline.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=quic_tdas@quicinc.com \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).