From: Zong Li <zong.li@sifive.com>
To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
palmer@dabbelt.com, paul.walmsley@sifive.com,
aou@eecs.berkeley.edu, greentime.hu@sifive.com,
conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Zong Li <zong.li@sifive.com>
Subject: [PATCH v5 1/7] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache
Date: Tue, 13 Sep 2022 06:18:11 +0000 [thread overview]
Message-ID: <20220913061817.22564-2-zong.li@sifive.com> (raw)
In-Reply-To: <20220913061817.22564-1-zong.li@sifive.com>
Since composable cache may be L3 cache if private L2 cache exists, we
should use its original name Composable cache to prevent confusion.
Signed-off-by: Zong Li <zong.li@sifive.com>
Suggested-by: Conor Dooley <conor.dooley@microchip.com>
Suggested-by: Ben Dooks <ben.dooks@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
...five-l2-cache.yaml => sifive,ccache0.yaml} | 28 +++++++++++++++----
1 file changed, 23 insertions(+), 5 deletions(-)
rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive,ccache0.yaml} (83%)
diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
similarity index 83%
rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
rename to Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
index ca3b9be58058..bf3f07421f7e 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
@@ -2,18 +2,18 @@
# Copyright (C) 2020 SiFive, Inc.
%YAML 1.2
---
-$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
+$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: SiFive L2 Cache Controller
+title: SiFive Composable Cache Controller
maintainers:
- Sagar Kadam <sagar.kadam@sifive.com>
- Paul Walmsley <paul.walmsley@sifive.com>
description:
- The SiFive Level 2 Cache Controller is used to provide access to fast copies
- of memory for masters in a Core Complex. The Level 2 Cache Controller also
+ The SiFive Composable Cache Controller is used to provide access to fast copies
+ of memory for masters in a Core Complex. The Composable Cache Controller also
acts as directory-based coherency manager.
All the properties in ePAPR/DeviceTree specification applies for this platform.
@@ -22,6 +22,7 @@ select:
compatible:
contains:
enum:
+ - sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
@@ -33,6 +34,7 @@ properties:
oneOf:
- items:
- enum:
+ - sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
- const: cache
@@ -45,7 +47,7 @@ properties:
const: 64
cache-level:
- const: 2
+ enum: [2, 3]
cache-sets:
enum: [1024, 2048]
@@ -115,6 +117,22 @@ allOf:
cache-sets:
const: 1024
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: sifive,ccache0
+
+ then:
+ properties:
+ cache-level:
+ enum: [2, 3]
+
+ else:
+ properties:
+ cache-level:
+ const: 2
+
additionalProperties: false
required:
--
2.17.1
next prev parent reply other threads:[~2022-09-13 6:18 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-13 6:18 [PATCH v5 0/7] Use composable cache instead of L2 cache Zong Li
2022-09-13 6:18 ` Zong Li [this message]
2022-09-13 6:18 ` [PATCH v5 2/7] soc: sifive: ccache: Rename SiFive L2 cache to Composable cache Zong Li
2022-09-13 6:18 ` [PATCH v5 3/7] soc: sifive: ccache: determine the cache level from dts Zong Li
2022-09-13 6:18 ` [PATCH v5 4/7] soc: sifive: ccache: reduce printing on init Zong Li
2022-09-13 6:18 ` [PATCH v5 5/7] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Zong Li
2022-09-13 6:18 ` [PATCH v5 6/7] soc: sifive: ccache: define the macro for the register shifts Zong Li
2022-09-13 6:18 ` [PATCH v5 7/7] riscv: Add cache information in AUX vector Zong Li
2022-09-13 10:34 ` Conor.Dooley
2022-09-21 5:09 ` [PATCH v5 0/7] Use composable cache instead of L2 cache Zong Li
2022-10-03 2:42 ` Zong Li
2022-10-04 14:20 ` Ben Dooks
2022-10-13 19:45 ` Palmer Dabbelt
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