From: Zong Li <zong.li@sifive.com>
To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
palmer@dabbelt.com, paul.walmsley@sifive.com,
aou@eecs.berkeley.edu, greentime.hu@sifive.com,
conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Zong Li <zong.li@sifive.com>
Subject: [PATCH v5 3/7] soc: sifive: ccache: determine the cache level from dts
Date: Tue, 13 Sep 2022 06:18:13 +0000 [thread overview]
Message-ID: <20220913061817.22564-4-zong.li@sifive.com> (raw)
In-Reply-To: <20220913061817.22564-1-zong.li@sifive.com>
Composable cache could be L2 or L3 cache, use 'cache-level' property of
device node to determine the level.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
drivers/soc/sifive/sifive_ccache.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index 949b824e89ad..b361b661ea09 100644
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -38,6 +38,7 @@
static void __iomem *ccache_base;
static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
static struct riscv_cacheinfo_ops ccache_cache_ops;
+static int level;
enum {
DIR_CORR = 0,
@@ -144,7 +145,7 @@ static const struct attribute_group *ccache_get_priv_group(struct cacheinfo
*this_leaf)
{
/* We want to use private group for composable cache only */
- if (this_leaf->level == 2)
+ if (this_leaf->level == level)
return &priv_attr_group;
else
return NULL;
@@ -215,6 +216,9 @@ static int __init sifive_ccache_init(void)
if (!ccache_base)
return -ENOMEM;
+ if (of_property_read_u32(np, "cache-level", &level))
+ return -ENOENT;
+
intr_num = of_property_count_u32_elems(np, "interrupts");
if (!intr_num) {
pr_err("CCACHE: no interrupts property\n");
--
2.17.1
next prev parent reply other threads:[~2022-09-13 6:19 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-13 6:18 [PATCH v5 0/7] Use composable cache instead of L2 cache Zong Li
2022-09-13 6:18 ` [PATCH v5 1/7] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Zong Li
2022-09-13 6:18 ` [PATCH v5 2/7] soc: sifive: ccache: Rename SiFive " Zong Li
2022-09-13 6:18 ` Zong Li [this message]
2022-09-13 6:18 ` [PATCH v5 4/7] soc: sifive: ccache: reduce printing on init Zong Li
2022-09-13 6:18 ` [PATCH v5 5/7] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Zong Li
2022-09-13 6:18 ` [PATCH v5 6/7] soc: sifive: ccache: define the macro for the register shifts Zong Li
2022-09-13 6:18 ` [PATCH v5 7/7] riscv: Add cache information in AUX vector Zong Li
2022-09-13 10:34 ` Conor.Dooley
2022-09-21 5:09 ` [PATCH v5 0/7] Use composable cache instead of L2 cache Zong Li
2022-10-03 2:42 ` Zong Li
2022-10-04 14:20 ` Ben Dooks
2022-10-13 19:45 ` Palmer Dabbelt
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