From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72AB2ECAAD3 for ; Wed, 14 Sep 2022 06:08:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229986AbiINGIF (ORCPT ); Wed, 14 Sep 2022 02:08:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229559AbiINGIB (ORCPT ); Wed, 14 Sep 2022 02:08:01 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BEAA2659E5; Tue, 13 Sep 2022 23:07:58 -0700 (PDT) X-UUID: 21431d0799bd48ba81502464e78511e3-20220914 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=6CC1heQJ2agAwz4rIPE+SNjcROSN6ODN9feKQXo2URA=; b=Kao/kMQNr1mot/Z6kWW1iJj/SXz8cHNp80hLragLvU+yC91+A3bxZAYbpkmTasvlAr91+NskYUiBr7CR0obNtABZb6/I4L/k25/OfUrHcmkar5hpeSCA9L9qFNQZ5YFYFHbuI96WnoSqQ1X3KEtYBepgzI/R9d7zVE+Fe5ZbzSo=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:7c18d72d-dd30-46e4-af07-31cd674cd808,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.11,REQID:7c18d72d-dd30-46e4-af07-31cd674cd808,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:39a5ff1,CLOUDID:b9a656f6-6e85-48d9-afd8-0504bbfe04cb,B ulkID:220914140755VSQUXU4M,BulkQuantity:0,Recheck:0,SF:28|17|19|48,TC:nil, Content:0,EDM:-3,IP:nil,URL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 21431d0799bd48ba81502464e78511e3-20220914 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1134585430; Wed, 14 Sep 2022 14:07:52 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 14 Sep 2022 14:07:51 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 14 Sep 2022 14:07:50 +0800 From: Chunfeng Yun To: Vinod Koul CC: Chunfeng Yun , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , , , , , , Eddie Hung , AngeloGioacchino Del Regno Subject: [PATCH v3 4/7] phy: phy-mtk-tphy: disable hardware efuse when set INTR Date: Wed, 14 Sep 2022 14:07:43 +0800 Message-ID: <20220914060746.10004-4-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220914060746.10004-1-chunfeng.yun@mediatek.com> References: <20220914060746.10004-1-chunfeng.yun@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org INTR's value is able autoload from hardware efuse by default, when software tries to update its value, should disable hardware efuse firstly. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Chunfeng Yun --- v3: add reviewed-by: AngeloGioacchino v2: no changes --- drivers/phy/mediatek/phy-mtk-tphy.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index 986fde0f63a0..7f40b8b052bd 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -874,9 +874,14 @@ static void u2_phy_props_set(struct mtk_tphy *tphy, mtk_phy_update_bits(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL, PA1_RG_TERM_SEL_VAL(instance->eye_term)); - if (instance->intr) + if (instance->intr) { + if (u2_banks->misc) + mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, + MR1_EFUSE_AUTO_LOAD_DIS); + mtk_phy_update_bits(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, PA1_RG_INTR_CAL_VAL(instance->intr)); + } if (instance->discth) mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, -- 2.18.0