From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FC07C6FA8A for ; Wed, 14 Sep 2022 06:08:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229997AbiINGIH (ORCPT ); Wed, 14 Sep 2022 02:08:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46224 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229903AbiINGIB (ORCPT ); Wed, 14 Sep 2022 02:08:01 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09B50659F0; Tue, 13 Sep 2022 23:07:59 -0700 (PDT) X-UUID: 537f1094018f42099cdfef34599cd6aa-20220914 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=xPbqDNwFmHbcjsXKUdDK3n8IBlxHgabye5RmFDQ3Mg4=; b=df9aw4kKt9+E+WacIWrZPCUP/ZgFgJxvxN9X+/Lt5lNSsKzCym9GyCEh9cE+h0BfW4gKt+kO6Ld48KagLCBVZNJGOu+qX6krjoucVIJE9XAzgfwsI4I6CspyaUY4g5b34PNDl7fwlkmp6yuEpvYCDERntQQTTdEW66oR8v3SQRs=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:b4f41815-24f6-4ca3-90a8-d6e56aa3848a,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.11,REQID:b4f41815-24f6-4ca3-90a8-d6e56aa3848a,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:39a5ff1,CLOUDID:cf94965d-5ed4-4e28-8b00-66ed9f042fbd,B ulkID:220914140756H924LX5C,BulkQuantity:0,Recheck:0,SF:28|17|19|48,TC:nil, Content:0,EDM:-3,IP:nil,URL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 537f1094018f42099cdfef34599cd6aa-20220914 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 876936124; Wed, 14 Sep 2022 14:07:55 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 14 Sep 2022 14:07:54 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 14 Sep 2022 14:07:53 +0800 From: Chunfeng Yun To: Vinod Koul CC: Chunfeng Yun , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , , , , , , Eddie Hung , AngeloGioacchino Del Regno Subject: [PATCH v3 7/7] phy: phy-mtk-tphy: fix the phy type setting issue Date: Wed, 14 Sep 2022 14:07:46 +0800 Message-ID: <20220914060746.10004-7-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220914060746.10004-1-chunfeng.yun@mediatek.com> References: <20220914060746.10004-1-chunfeng.yun@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The PHY type is not set if the index is non zero, prepare type value according to the index, like as mask value. Fixes: 39099a443358 ("phy: phy-mtk-tphy: support type switch by pericfg") Signed-off-by: Chunfeng Yun --- v3: add fixes tag suggested by AngeloGioacchino v2: no changes --- drivers/phy/mediatek/phy-mtk-tphy.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index e0f227a0d3cc..cc10298bc70d 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -915,7 +915,7 @@ static int phy_type_syscon_get(struct mtk_phy_instance *instance, static int phy_type_set(struct mtk_phy_instance *instance) { int type; - u32 mask; + u32 offset; if (!instance->type_sw) return 0; @@ -938,8 +938,9 @@ static int phy_type_set(struct mtk_phy_instance *instance) return 0; } - mask = RG_PHY_SW_TYPE << (instance->type_sw_index * BITS_PER_BYTE); - regmap_update_bits(instance->type_sw, instance->type_sw_reg, mask, type); + offset = instance->type_sw_index * BITS_PER_BYTE; + regmap_update_bits(instance->type_sw, instance->type_sw_reg, + RG_PHY_SW_TYPE << offset, type << offset); return 0; } -- 2.18.0