From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67D90ECAAD3 for ; Wed, 14 Sep 2022 12:46:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229885AbiINMqL (ORCPT ); Wed, 14 Sep 2022 08:46:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229503AbiINMqI (ORCPT ); Wed, 14 Sep 2022 08:46:08 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9CA3796A5; Wed, 14 Sep 2022 05:46:00 -0700 (PDT) X-UUID: ab88dfb6068b477bbb2b45efc767d0ab-20220914 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=aUZWTs4n4ys6gRZNfBS5r6NVuRwpcI3HfWmJC/NvUBs=; b=m8EfpTAsxrRVLL8uPyxx8xS1Ks2ReKLVrAWpZ2Aw+Br4/djN5tdnOFf0RlFLqWlV5m6RMQjhUdgNZnOg/FO1htDwK15spgEyGt24DAsnwZqqAmFnqeQ+d+Ftz/SwzkQJ/ES3SbedJPStH0GFFcQmX3stbhyUOhftTSO9xzyY0F8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:cc37958e-fb46-412f-8f25-28e222328fce,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:70 X-CID-INFO: VERSION:1.1.11,REQID:cc37958e-fb46-412f-8f25-28e222328fce,IP:0,URL :0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:70 X-CID-META: VersionHash:39a5ff1,CLOUDID:81aa63f6-6e85-48d9-afd8-0504bbfe04cb,B ulkID:22091420455628VDJZF5,BulkQuantity:0,Recheck:0,SF:28|17|19|48,TC:nil, Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: ab88dfb6068b477bbb2b45efc767d0ab-20220914 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 674760164; Wed, 14 Sep 2022 20:45:55 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 14 Sep 2022 20:45:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 14 Sep 2022 20:45:53 +0800 From: Johnson Wang To: , , , CC: , , , , , , Johnson Wang Subject: [PATCH v2 0/4] Introduce MediaTek frequency hopping driver Date: Wed, 14 Sep 2022 20:45:48 +0800 Message-ID: <20220914124552.16964-1-johnson.wang@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The purpose of this serie is to enhance frequency hopping and spread spectrum clocking feature for MT8186. We introduce new PLL register APIs and some helpers for FHCTL hardware control. For MT8186 PLL driver, we replace mtk_clk_register_plls() with newly added API to support frequency hopping and SSC function for specific PLLs. Changes in v2: - Use SoC-specific compatible instead of generic one. - Use standard clocks property and vendor-specific property in dt-binding. - Remove some unused arguments and fix some coding style. Johnson Wang (4): clk: mediatek: Export PLL operations symbols dt-bindings: arm: mediatek: Add new bindings of MediaTek frequency hopping clk: mediatek: Add new clock driver to handle FHCTL hardware clk: mediatek: Change PLL register API for MT8186 .../bindings/arm/mediatek/mediatek,fhctl.yaml | 47 +++ drivers/clk/mediatek/Makefile | 2 +- drivers/clk/mediatek/clk-fhctl.c | 244 ++++++++++++++++ drivers/clk/mediatek/clk-fhctl.h | 26 ++ drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 66 ++++- drivers/clk/mediatek/clk-pll.c | 84 +++--- drivers/clk/mediatek/clk-pll.h | 56 ++++ drivers/clk/mediatek/clk-pllfh.c | 268 ++++++++++++++++++ drivers/clk/mediatek/clk-pllfh.h | 82 ++++++ 9 files changed, 821 insertions(+), 54 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yaml create mode 100644 drivers/clk/mediatek/clk-fhctl.c create mode 100644 drivers/clk/mediatek/clk-fhctl.h create mode 100644 drivers/clk/mediatek/clk-pllfh.c create mode 100644 drivers/clk/mediatek/clk-pllfh.h -- 2.18.0