From: Conor Dooley <conor.dooley@microchip.com>
To: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor.dooley@microchip.com>,
Daire McNamara <daire.mcnamara@microchip.com>,
Shravan Chippa <shravan.chippa@microchip.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Cyril Jean <Cyril.Jean@microchip.com>,
Lewis Hanly <lewis.hanly@microchip.com>,
Vattipalli Praveen <praveen.kumar@microchip.com>,
Wolfgang Grandegger <wg@aries-embedded.de>,
Hugh Breslin <hugh.breslin@microchip.com>,
<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, Rob Herring <robh@kernel.org>
Subject: [PATCH v5 02/10] dt-bindings: riscv: microchip: document the aries m100pfsevp
Date: Fri, 16 Sep 2022 12:26:38 +0100 [thread overview]
Message-ID: <20220916112645.567794-3-conor.dooley@microchip.com> (raw)
In-Reply-To: <20220916112645.567794-1-conor.dooley@microchip.com>
Add a compatible for the Aries Embedded M100PFSEVP SOM + EVK platform.
Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-som-mpfs025t-pcie-serdes
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/riscv/microchip.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 485981fbfb4b..630f82c85a0c 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -27,6 +27,7 @@ properties:
- items:
- enum:
+ - aries,m100pfsevp
- sundance,polarberry
- const: microchip,mpfs
--
2.36.1
next prev parent reply other threads:[~2022-09-16 11:27 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-16 11:26 [PATCH v5 00/10] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
2022-09-16 11:26 ` [PATCH v5 01/10] dt-bindings: riscv: microchip: document icicle reference design Conor Dooley
2022-09-16 11:26 ` Conor Dooley [this message]
2022-09-16 11:26 ` [PATCH v5 03/10] dt-bindings: riscv: microchip: document the sev kit Conor Dooley
2022-09-16 11:26 ` [PATCH v5 04/10] riscv: dts: microchip: add pci dma ranges for the icicle kit Conor Dooley
2022-09-16 11:26 ` [PATCH v5 05/10] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi Conor Dooley
2022-09-16 11:26 ` [PATCH v5 06/10] riscv: dts: microchip: icicle: update pci address properties Conor Dooley
2022-09-16 11:26 ` [PATCH v5 07/10] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses Conor Dooley
2022-09-16 11:26 ` [PATCH v5 08/10] riscv: dts: microchip: reduce the fic3 clock rate Conor Dooley
2022-09-16 11:26 ` [PATCH v5 09/10] riscv: dts: microchip: add sevkit device tree Conor Dooley
2022-09-16 11:26 ` [PATCH v5 10/10] riscv: dts: microchip: add a devicetree for aries' m100pfsevp Conor Dooley
2022-09-19 18:22 ` [PATCH v5 00/10] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220916112645.567794-3-conor.dooley@microchip.com \
--to=conor.dooley@microchip.com \
--cc=Cyril.Jean@microchip.com \
--cc=aou@eecs.berkeley.edu \
--cc=daire.mcnamara@microchip.com \
--cc=devicetree@vger.kernel.org \
--cc=hugh.breslin@microchip.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=lewis.hanly@microchip.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=praveen.kumar@microchip.com \
--cc=robh+dt@kernel.org \
--cc=robh@kernel.org \
--cc=shravan.chippa@microchip.com \
--cc=wg@aries-embedded.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).