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Mon, 19 Sep 2022 07:15:02 -0700 From: Sandipan Patra To: , , , , , , CC: , , Sandipan Patra Subject: [PATCH v5 2/3] arm64: tegra: Add PWM controllers on Tegra234 Date: Mon, 19 Sep 2022 19:44:54 +0530 Message-ID: <20220919141455.31084-2-spatra@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220919141455.31084-1-spatra@nvidia.com> References: <20220919141455.31084-1-spatra@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT055:EE_|BL1PR12MB5333:EE_ X-MS-Office365-Filtering-Correlation-Id: e106abf9-ea59-4992-0b11-08da9a496159 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8Bj+dFvWlJ8ZmfvfWRtTAsqtKCLIs7VxVs++HmTw8hHMg90DajOR1Bwnk+wWb+00uCz+xxKjWXmesDaKFiJ7bz07EM58Pza2OzeKs7HIc7RTOfQKqVxbQRj6INXXeI+nHgo2fCQ2lohzEuJBav6Y6Kt1IFQ7T7KwY9E4bYSXG/sftfwEZivtofvLIdh7KFjBBLCpTrY4EZeBULqsudEB5N5zSpwC8EVlAXie79N59pEEX6Nipiv9FDF7j0/s/uWl+mOQ7ElHLdygMpF62le+juw0y5wmAXeHrti4dJEGah8y1c+k0yoVi1lFbc+RkheIlFvPHA32r9NQUdmNRRpFpH+vVIY3lMVX05SBsl5MTdwt31SCF/cfFBlAA1T9q1dyXm7HbBnYEYWiuokus59GN+rMxaMyIRvgsKhV3qtbcySjc4iGiUIt+3IomwsxGHOBRuNg82vSOoyR2bwoUygLHs+OL1dz70bm8sAXV+ZwiCKX2bH/DYM+nlTHHF/cuzXlewM7r6X1ODnVS30uXmvwSPmcpVEDM56607GqNkx7CkVDaudd+HTor4FeT06AusC73O7D6t7rPYRdSB5M4qdXklCRsuV8fYyxgiiVPErybkAybq+XXF6V4LVFRxt1unY5BkM0ouNMQN2a/gO5nV6wInrtZJpEAbKMYFNWgTDnvh8Ky5mIz/X7qUKUAhcJEDrfBuFnHsOAI4NNgT6/hGSxMG/vhHLvDF/dyYHTgLCBDlLrxfRiIQNCtblExhdHBeOcRCuFNplEc6rzz/a1ERjdvmiVreN+sj2159inryk/oIeA+xq6yeM7WtIZw0OvvDiC X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(396003)(376002)(136003)(346002)(451199015)(46966006)(40470700004)(36840700001)(36860700001)(36756003)(86362001)(82740400003)(7636003)(40480700001)(356005)(40460700003)(316002)(8676002)(110136005)(54906003)(2906002)(70586007)(4326008)(5660300002)(41300700001)(8936002)(70206006)(83380400001)(2616005)(426003)(336012)(82310400005)(186003)(1076003)(47076005)(6666004)(107886003)(478600001)(26005)(7696005)(16060500005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Sep 2022 14:15:18.0830 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e106abf9-ea59-4992-0b11-08da9a496159 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5333 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra234 has eight single-channel PWM controllers, one of them in the AON block. Signed-off-by: Sandipan Patra --- V4->V5: Update compatable with Tegra234 and fallback arch/arm64/boot/dts/nvidia/tegra234.dtsi | 88 +++++++++++++++++++++++- 1 file changed, 86 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 0170bfa8a467..b1b29e3c207c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -870,8 +870,8 @@ }; pwm1: pwm@3280000 { - compatible = "nvidia,tegra194-pwm", - "nvidia,tegra186-pwm"; + compatible = "nvidia,tegra234-pwm", + "nvidia,tegra194-pwm"; reg = <0x3280000 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM1>; clock-names = "pwm"; @@ -881,6 +881,90 @@ #pwm-cells = <2>; }; + pwm2: pwm@3290000 { + compatible = "nvidia,tegra234-pwm", + "nvidia,tegra194-pwm"; + reg = <0x3290000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM2>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM2>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm3: pwm@32a0000 { + compatible = "nvidia,tegra234-pwm", + "nvidia,tegra194-pwm"; + reg = <0x32a0000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM3>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM3>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm4: pwm@c340000 { + compatible = "nvidia,tegra234-pwm", + "nvidia,tegra194-pwm"; + reg = <0xc340000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM4>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM4>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm5: pwm@32c0000 { + compatible = "nvidia,tegra234-pwm", + "nvidia,tegra194-pwm"; + reg = <0x32c0000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM5>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM5>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm6: pwm@32d0000 { + compatible = "nvidia,tegra234-pwm", + "nvidia,tegra194-pwm"; + reg = <0x32d0000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM6>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM6>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm7: pwm@32e0000 { + compatible = "nvidia,tegra234-pwm", + "nvidia,tegra194-pwm"; + reg = <0x32e0000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM7>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM7>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm8: pwm@32f0000 { + compatible = "nvidia,tegra234-pwm", + "nvidia,tegra194-pwm"; + reg = <0x32f0000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM8>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM8>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + spi@3300000 { compatible = "nvidia,tegra234-qspi"; reg = <0x3300000 0x1000>; -- 2.17.1