From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B8B6C6FA90 for ; Wed, 28 Sep 2022 15:00:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234671AbiI1PAm (ORCPT ); Wed, 28 Sep 2022 11:00:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234672AbiI1PAQ (ORCPT ); Wed, 28 Sep 2022 11:00:16 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55CC9193F6 for ; Wed, 28 Sep 2022 08:00:07 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id k10so20796361lfm.4 for ; Wed, 28 Sep 2022 08:00:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=2kS0hYpfUuaV5KsEXWP/lDx5+l6PN7wJvPgJ9tbwDA0=; b=VAdhQctFQWioF74NOD+w0YCv2zXqaN7FG2NsGtHhYaMv8RQ84zudprxk1PyLom9qII 0v0L9+olIGVOLnhXRSwyAwQfKtlkon475K5rpgY29+FLRfFi494K6gD7EDq9U+drGES2 DaEONXlWtNJD5mkC696AqT5R3JaVHIEME8puAjxvWxnTqCYWLXKb5sq380pm68M3ogcL ewG8WOl5qjuDNep7TUUd2WOl4joxXZfpIvDzGzt9cW4vd3M427yUfnRZGwv5n1mMTl0V KpS6MW3dDHsiJefQvyBgGQfzcXGCGypwJ/GiPLLJ0HqZTzgDOgJMf4ZjLEEZR+R81rT3 yV0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=2kS0hYpfUuaV5KsEXWP/lDx5+l6PN7wJvPgJ9tbwDA0=; b=rpE7eDHqG4vBC0cA5s2yMX1KrQEIIQWFgIO0IE+ZJYUHYf8SfDzslQgnN8jOHWhGJK sBt9ugekfVBNT0Uzt7bNyw02fNi5XcgfTObW49yAcA/+esW3D7rVakdIaQakmbu/yGWh XCyvF3p1g/DTJ6PmsBjd7brbqB2TWmbJgOnaZBTu08uFBf4p3IuQri8N2kU8GgvtDunA Nvxxb7jR38bcW3pJg2yhVXjxxrf8imkT6Jm1Kyvm54x8mr9aYMaSBT2+UsolRtJVrEBP Cg61ynEqsUEUiVJHSzz/Rnh2LnWOZJig3pXGdxBNcq3j3IE4m9A+0PZr3hqZ05gDAF4D LL2g== X-Gm-Message-State: ACrzQf0rSHCHw9wPyQN7M/TauVWIdwSinO8ggl+olA/SvjF3V+EdgitK cvPGSbTwUyuhTQz7mtILbdHcvg== X-Google-Smtp-Source: AMsMyM6eL21ikLeJe9RQLblnMtEquUYoNpyQFgXtRpsYmgL4Nks6/l3Iz3SE9fNIIGR44cxOmbluzA== X-Received: by 2002:a05:6512:c13:b0:49f:9a2f:8b86 with SMTP id z19-20020a0565120c1300b0049f9a2f8b86mr13198508lfu.413.1664377204439; Wed, 28 Sep 2022 08:00:04 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id be36-20020a056512252400b00492c017de43sm494996lfb.127.2022.09.28.08.00.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Sep 2022 08:00:04 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 06/11] clk: qcom: mmcc-msm8974: use ARRAY_SIZE instead of specifying num_parents Date: Wed, 28 Sep 2022 17:59:53 +0300 Message-Id: <20220928145958.376288-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> References: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/mmcc-msm8974.c | 74 ++++++++++++++++----------------- 1 file changed, 37 insertions(+), 37 deletions(-) diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c index f74662925a58..9008df2305df 100644 --- a/drivers/clk/qcom/mmcc-msm8974.c +++ b/drivers/clk/qcom/mmcc-msm8974.c @@ -252,7 +252,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mmss_ahb_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -289,7 +289,7 @@ static struct clk_rcg2 mmss_axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mmss_axi_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -313,7 +313,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "ocmemnoc_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -332,7 +332,7 @@ static struct clk_rcg2 csi0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi0_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -345,7 +345,7 @@ static struct clk_rcg2 csi1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi1_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -358,7 +358,7 @@ static struct clk_rcg2 csi2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi2_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -371,7 +371,7 @@ static struct clk_rcg2 csi3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi3_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -418,7 +418,7 @@ static struct clk_rcg2 vfe0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vfe0_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -431,7 +431,7 @@ static struct clk_rcg2 vfe1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vfe1_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -472,7 +472,7 @@ static struct clk_rcg2 mdp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mdp_clk_src", .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -495,7 +495,7 @@ static struct clk_rcg2 jpeg0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "jpeg0_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -508,7 +508,7 @@ static struct clk_rcg2 jpeg1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "jpeg1_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -521,7 +521,7 @@ static struct clk_rcg2 jpeg2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "jpeg2_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -534,7 +534,7 @@ static struct clk_rcg2 pclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pclk0_clk_src", .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), .ops = &clk_pixel_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -548,7 +548,7 @@ static struct clk_rcg2 pclk1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pclk1_clk_src", .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), .ops = &clk_pixel_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -581,7 +581,7 @@ static struct clk_rcg2 vcodec0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vcodec0_clk_src", .parent_names = mmcc_xo_mmpll0_1_3_gpll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -599,7 +599,7 @@ static struct clk_rcg2 cci_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cci_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -623,7 +623,7 @@ static struct clk_rcg2 camss_gp0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "camss_gp0_clk_src", .parent_names = mmcc_xo_mmpll0_1_gpll1_0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0), .ops = &clk_rcg2_ops, }, }; @@ -637,7 +637,7 @@ static struct clk_rcg2 camss_gp1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "camss_gp1_clk_src", .parent_names = mmcc_xo_mmpll0_1_gpll1_0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0), .ops = &clk_rcg2_ops, }, }; @@ -672,7 +672,7 @@ static struct clk_rcg2 mclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mclk0_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -685,7 +685,7 @@ static struct clk_rcg2 mclk1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mclk1_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -698,7 +698,7 @@ static struct clk_rcg2 mclk2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mclk2_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -711,7 +711,7 @@ static struct clk_rcg2 mclk3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mclk3_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -730,7 +730,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi0phytimer_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -743,7 +743,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi1phytimer_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -756,7 +756,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi2phytimer_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -787,7 +787,7 @@ static struct clk_rcg2 cpp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cpp_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -805,7 +805,7 @@ static struct clk_rcg2 byte0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "byte0_clk_src", .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -819,7 +819,7 @@ static struct clk_rcg2 byte1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "byte1_clk_src", .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -838,7 +838,7 @@ static struct clk_rcg2 edpaux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "edpaux_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -857,7 +857,7 @@ static struct clk_rcg2 edplink_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "edplink_clk_src", .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), .ops = &clk_rcg2_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -877,7 +877,7 @@ static struct clk_rcg2 edppixel_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "edppixel_clk_src", .parent_names = mmcc_xo_dsi_hdmi_edp, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp), .ops = &clk_edp_pixel_ops, }, }; @@ -895,7 +895,7 @@ static struct clk_rcg2 esc0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "esc0_clk_src", .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -908,7 +908,7 @@ static struct clk_rcg2 esc1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "esc1_clk_src", .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -926,7 +926,7 @@ static struct clk_rcg2 extpclk_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "extpclk_clk_src", .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), .ops = &clk_byte_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -945,7 +945,7 @@ static struct clk_rcg2 hdmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "hdmi_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -963,7 +963,7 @@ static struct clk_rcg2 vsync_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vsync_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; -- 2.35.1