From: Dinh Nguyen <dinguyen@kernel.org>
To: jh80.chung@samsung.com
Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, linux-mmc@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: [PATCHv4 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon"
Date: Wed, 28 Sep 2022 11:54:18 -0500 [thread overview]
Message-ID: <20220928165420.1212284-1-dinguyen@kernel.org> (raw)
Document the optional "altr,sysmgr-syscon" binding that is used to
access the System Manager register that controls the SDMMC clock
phase.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v4: add else statement
v3: document that the "altr,sysmgr-syscon" binding is only applicable to
"altr,socfpga-dw-mshc"
v2: document "altr,sysmgr-syscon" in the MMC section
---
.../bindings/mmc/synopsys-dw-mshc.yaml | 31 +++++++++++++++++--
1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
index ae6d6fca79e2..b73324273464 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
@@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys Designware Mobile Storage Host Controller Binding
-allOf:
- - $ref: "synopsys-dw-mshc-common.yaml#"
-
maintainers:
- Ulf Hansson <ulf.hansson@linaro.org>
@@ -38,6 +35,34 @@ properties:
- const: biu
- const: ciu
+ altr,sysmgr-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to the sysmgr node
+ - description: register offset that controls the SDMMC clock phase
+ description:
+ Contains the phandle to System Manager block that contains
+ the SDMMC clock-phase control register. The first value is the pointer
+ to the sysmgr and the 2nd value is the register offset for the SDMMC
+ clock phase register.
+
+allOf:
+ - $ref: "synopsys-dw-mshc-common.yaml#"
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const:
+ - altr,socfpga-dw-mshc
+ then:
+ required:
+ - altr,sysmgr-syscon
+ else:
+ properties:
+ altr,sysmgr-syscon: false
+
required:
- compatible
- reg
--
2.25.1
next reply other threads:[~2022-09-28 16:54 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-28 16:54 Dinh Nguyen [this message]
2022-09-28 16:54 ` [PATCHv4 2/3] arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node Dinh Nguyen
2022-09-28 16:54 ` [PATCHv4 3/3] mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase Dinh Nguyen
2022-09-29 11:20 ` Ulf Hansson
2022-09-28 17:15 ` [PATCHv4 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Krzysztof Kozlowski
2022-09-28 18:37 ` Dinh Nguyen
2022-09-29 6:49 ` Krzysztof Kozlowski
2022-09-28 22:37 ` Rob Herring
2022-09-29 9:24 ` Ulf Hansson
2022-09-29 9:38 ` Krzysztof Kozlowski
2022-09-29 11:04 ` Ulf Hansson
2022-09-29 11:13 ` Krzysztof Kozlowski
2022-09-29 14:20 ` Dinh Nguyen
2022-09-29 14:38 ` Krzysztof Kozlowski
2022-09-29 15:18 ` Dinh Nguyen
2022-10-01 10:06 ` Krzysztof Kozlowski
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