From: Johnson Wang <johnson.wang@mediatek.com>
To: <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<angelogioacchino.delregno@collabora.com>, <sboyd@kernel.org>
Cc: <linux-clk@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
<kuan-hsin.lee@mediatek.com>, <yu-chang.wang@mediatek.com>,
Johnson Wang <johnson.wang@mediatek.com>
Subject: [PATCH v3 0/4] Introduce MediaTek frequency hopping driver
Date: Thu, 29 Sep 2022 19:46:20 +0800 [thread overview]
Message-ID: <20220929114624.16809-1-johnson.wang@mediatek.com> (raw)
The purpose of this serie is to enhance frequency hopping and spread spectrum
clocking feature for MT8186.
We introduce new PLL register APIs and some helpers for FHCTL hardware control.
For MT8186 PLL driver, we replace mtk_clk_register_plls() with newly added API
to support frequency hopping and SSC function for specific PLLs.
Changes in v3:
- Change binding file name.
- Add some constraints for properties.
- Rename "mediatek,hopping-ssc-percents" to "mediatek,hopping-ssc-percent".
- Add new config symbol.
Changes in v2:
- Use SoC-specific compatible instead of generic one.
- Use standard clocks property and vendor-specific property in dt-binding.
- Remove some unused arguments and fix some coding style.
Johnson Wang (4):
clk: mediatek: Export PLL operations symbols
dt-bindings: arm: mediatek: Add new bindings of MediaTek frequency
hopping
clk: mediatek: Add new clock driver to handle FHCTL hardware
clk: mediatek: Change PLL register API for MT8186
.../arm/mediatek/mediatek,mt8186-fhctl.yaml | 53 ++++
drivers/clk/mediatek/Kconfig | 8 +
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-fhctl.c | 244 ++++++++++++++++
drivers/clk/mediatek/clk-fhctl.h | 26 ++
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 66 ++++-
drivers/clk/mediatek/clk-pll.c | 84 +++---
drivers/clk/mediatek/clk-pll.h | 56 ++++
drivers/clk/mediatek/clk-pllfh.c | 268 ++++++++++++++++++
drivers/clk/mediatek/clk-pllfh.h | 82 ++++++
10 files changed, 835 insertions(+), 53 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-fhctl.yaml
create mode 100644 drivers/clk/mediatek/clk-fhctl.c
create mode 100644 drivers/clk/mediatek/clk-fhctl.h
create mode 100644 drivers/clk/mediatek/clk-pllfh.c
create mode 100644 drivers/clk/mediatek/clk-pllfh.h
--
2.18.0
next reply other threads:[~2022-09-29 11:46 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-29 11:46 Johnson Wang [this message]
2022-09-29 11:46 ` [PATCH v3 1/4] clk: mediatek: Export PLL operations symbols Johnson Wang
2022-09-29 13:07 ` AngeloGioacchino Del Regno
2022-10-06 11:24 ` Johnson Wang (王聖鑫)
2022-09-29 11:46 ` [PATCH v3 2/4] dt-bindings: arm: mediatek: Add new bindings of MediaTek frequency hopping Johnson Wang
2022-09-29 13:07 ` AngeloGioacchino Del Regno
2022-09-30 19:07 ` Rob Herring
2022-10-06 11:23 ` Johnson Wang (王聖鑫)
2022-10-06 12:33 ` AngeloGioacchino Del Regno
2022-10-11 6:55 ` Johnson Wang (王聖鑫)
2022-09-30 19:07 ` Rob Herring
2022-09-29 11:46 ` [PATCH v3 3/4] clk: mediatek: Add new clock driver to handle FHCTL hardware Johnson Wang
2022-09-29 11:46 ` [PATCH v3 4/4] clk: mediatek: Change PLL register API for MT8186 Johnson Wang
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