From: Rob Herring <robh@kernel.org>
To: Biju Das <biju.das.jz@bp.renesas.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Lee Jones <lee@kernel.org>,
devicetree@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH RFC 2/7] dt-bindings: mfd: rzg2l-mtu3: Document RZ/G2L MTU3 counter
Date: Fri, 30 Sep 2022 14:03:11 -0500 [thread overview]
Message-ID: <20220930190311.GA651384-robh@kernel.org> (raw)
In-Reply-To: <20220929103043.1228235-3-biju.das.jz@bp.renesas.com>
On Thu, Sep 29, 2022 at 11:30:38AM +0100, Biju Das wrote:
> Document 16-bit and 32-bit phase counting mode support on
> RZ/G2L MTU3 IP.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> * Updated commit header.
> ---
> .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 35 +++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> index c1fae8e8d9f9..c4bcf28623d6 100644
> --- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
> @@ -192,6 +192,37 @@ properties:
> "#size-cells":
> const: 0
>
> +patternProperties:
> + "^counter@[1-2]+$":
> + type: object
> +
> + properties:
> + compatible:
> + const: renesas,rzg2l-mtu3-counter
> +
> + reg:
> + description: Identify counter channels.
> + items:
> + enum: [ 1, 2 ]
> +
> + renesas,32bit-phase-counting:
> + type: boolean
> + description: Enable 32-bit phase counting mode.
> +
> + renesas,ext-input-phase-clock-select:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [ 0, 1 ]
> + default: 1
> + description: |
> + Selects the external clock pin for phase counting mode.
> + <0> : MTCLKA and MTCLKB are selected for the external phase clock.
> + <1> : MTCLKC and MTCLKD are selected for the external phase clock
> + (default)
Why do these belong in DT?
> +
> + required:
> + - compatible
> + - reg
> +
> required:
> - compatible
> - reg
> @@ -270,6 +301,10 @@ examples:
> clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
> power-domains = <&cpg>;
> resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
> + counter@1 {
> + compatible = "renesas,rzg2l-mtu3-counter";
> + reg = <1>;
> + };
> };
>
> ...
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2022-09-30 19:03 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-29 10:30 [PATCH RFC 0/7] Add RZ/G2L MTU3 PWM driver Biju Das
2022-09-29 10:30 ` [PATCH RFC 1/7] dt-bindings: mfd: Document RZ/G2L MTU3a bindings Biju Das
2022-09-29 17:53 ` Lee Jones
2022-09-30 17:47 ` Rob Herring
2022-10-03 7:34 ` Lee Jones
2022-10-03 7:38 ` Geert Uytterhoeven
2022-10-03 8:51 ` Lee Jones
2022-09-29 10:30 ` [PATCH RFC 2/7] dt-bindings: mfd: rzg2l-mtu3: Document RZ/G2L MTU3 counter Biju Das
2022-09-29 17:52 ` Lee Jones
2022-09-30 19:03 ` Rob Herring [this message]
2022-10-01 16:36 ` Biju Das
2022-10-02 16:50 ` Biju Das
2022-09-29 10:30 ` [PATCH RFC 3/7] dt-bindings: mfd: rz-mtu3: Document RZ/G2L MTU3 PWM Biju Das
2022-09-29 17:52 ` Lee Jones
2022-09-29 17:59 ` Biju Das
2022-09-30 12:10 ` Lee Jones
2022-10-01 19:26 ` Biju Das
2022-10-03 7:32 ` Lee Jones
2022-10-03 8:16 ` Biju Das
2022-10-03 8:57 ` Lee Jones
2022-10-03 9:04 ` Biju Das
2022-10-03 9:34 ` Biju Das
2022-09-30 18:35 ` Rob Herring
2022-10-01 16:30 ` Biju Das
2022-09-29 10:30 ` [PATCH RFC 5/7] arm64: dts: renesas: r9a07g044: Add MTU3 PWM support Biju Das
2022-09-29 10:30 ` [PATCH RFC 6/7] arm64: dts: renesas: r9a07g054: " Biju Das
2022-09-29 10:30 ` [PATCH RFC 7/7] arm64: dts: renesas: rzg2l-smarc: [HACK] Enable MTU3 PWM channel 3 for PWM mode 1 testing Biju Das
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