* [PATCH v6 0/3] iommu/mediatek: Add mt8365 iommu support
@ 2022-11-02 15:18 Alexandre Mergnat
2022-11-02 15:18 ` [PATCH v6 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC Alexandre Mergnat
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Alexandre Mergnat @ 2022-11-02 15:18 UTC (permalink / raw)
To: Matthias Brugger, Krzysztof Kozlowski, Joerg Roedel, Rob Herring,
Robin Murphy, Will Deacon, Yong Wu
Cc: linux-kernel, Alexandre Mergnat, iommu, linux-mediatek,
Amjad Ouled-Ameur, Markus Schneider-Pargmann, linux-arm-kernel,
Fabien Parent, AngeloGioacchino Del Regno, devicetree,
Krzysztof Kozlowski
Hi,
This series contains patches related to the support of mt8365 iommu.
Thanks for your feedback so far.
Regards,
Alex
Changes in v6:
- Rebase
- Add new trailers
- Link to v5: https://lore.kernel.org/r/20221001-iommu-support-v5-0-92cdbb83bbb8@baylibre.com
Changes in v5:
- Fix name file in mediatek,iommu.yaml
- Rename defines to be more consistent
- Rework INT_ID_PORT_WIDTH_6 check
- Link to v4: https://lore.kernel.org/r/20221001-iommu-support-v4-0-f1e13438dfd2@baylibre.com
Changes in v4:
- Typo
- Rebase
- Link to v3: https://lore.kernel.org/r/20221001-iommu-support-v3-0-c7b3059b0d16@baylibre.com
Changes in v3:
- Rename "mt8365-larb-port.h" to "mediatek,mt8365-larb-port.h"
- Rework the macros which retrieve larb/port ID to improve human readability
- Link to v2: https://lore.kernel.org/r/20221001-iommu-support-v2-0-dbfef2eeebc9@baylibre.com
Changes in v2:
- Rebase.
- Change M4U_PORT_APU_READ & M4U_PORT_APU_WRITE port to avoid display
conflict in larb0. These definitions are used for vpu0 device node.
- Add dual license.
- Retitle commit.
- Rename to int_id_port_width for more detail.
- Fix typo.
- Set banks_enable and banks_num in mt8365_data to fix kernel panic at boot.
- Link to v1 - https://lore.kernel.org/lkml/20220530180328.845692-1-fparent@baylibre.com/
To: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>
To: Will Deacon <will@kernel.org>
To: Robin Murphy <robin.murphy@arm.com>
To: Rob Herring <robh+dt@kernel.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
To: Matthias Brugger <matthias.bgg@gmail.com>
Cc: iommu@lists.linux.dev
Cc: linux-mediatek@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: Fabien Parent <fparent@baylibre.com>
Cc: Markus Schneider-Pargmann <msp@baylibre.com>
Cc: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
---
Fabien Parent (3):
dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC
iommu/mediatek: add support for 6-bit encoded port IDs
iommu/mediatek: add support for MT8365 SoC
.../devicetree/bindings/iommu/mediatek,iommu.yaml | 2 +
drivers/iommu/mtk_iommu.c | 25 +++++-
.../dt-bindings/memory/mediatek,mt8365-larb-port.h | 90 ++++++++++++++++++++++
3 files changed, 116 insertions(+), 1 deletion(-)
---
base-commit: 11082343e3bf2953a937509f0316cabf69dbf908
change-id: 20221001-iommu-support-f409c7e094e6
Best regards,
--
Alexandre Mergnat <amergnat@baylibre.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v6 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC
2022-11-02 15:18 [PATCH v6 0/3] iommu/mediatek: Add mt8365 iommu support Alexandre Mergnat
@ 2022-11-02 15:18 ` Alexandre Mergnat
2022-11-02 15:18 ` [PATCH v6 2/3] iommu/mediatek: add support for 6-bit encoded port IDs Alexandre Mergnat
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Alexandre Mergnat @ 2022-11-02 15:18 UTC (permalink / raw)
To: Matthias Brugger, Krzysztof Kozlowski, Joerg Roedel, Rob Herring,
Robin Murphy, Will Deacon, Yong Wu
Cc: linux-kernel, Alexandre Mergnat, iommu, linux-mediatek,
Amjad Ouled-Ameur, Markus Schneider-Pargmann, linux-arm-kernel,
Fabien Parent, AngeloGioacchino Del Regno, devicetree,
Krzysztof Kozlowski
From: Fabien Parent <fparent@baylibre.com>
Add IOMMU binding documentation for the MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
---
.../devicetree/bindings/iommu/mediatek,iommu.yaml | 2 +
.../dt-bindings/memory/mediatek,mt8365-larb-port.h | 90 ++++++++++++++++++++++
2 files changed, 92 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
index fee0241b5098..725434d9d646 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
@@ -81,6 +81,7 @@ properties:
- mediatek,mt8195-iommu-vdo # generation two
- mediatek,mt8195-iommu-vpp # generation two
- mediatek,mt8195-iommu-infra # generation two
+ - mediatek,mt8365-m4u # generation two
- description: mt7623 generation one
items:
@@ -130,6 +131,7 @@ properties:
dt-binding/memory/mt8186-memory-port.h for mt8186,
dt-binding/memory/mt8192-larb-port.h for mt8192.
dt-binding/memory/mt8195-memory-port.h for mt8195.
+ dt-binding/memory/mediatek,mt8365-larb-port.h for mt8365.
power-domains:
maxItems: 1
diff --git a/include/dt-bindings/memory/mediatek,mt8365-larb-port.h b/include/dt-bindings/memory/mediatek,mt8365-larb-port.h
new file mode 100644
index 000000000000..56d5a5dd519e
--- /dev/null
+++ b/include/dt-bindings/memory/mediatek,mt8365-larb-port.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Yong Wu <yong.wu@mediatek.com>
+ */
+#ifndef _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_
+#define _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_
+
+#include <dt-bindings/memory/mtk-memory-port.h>
+
+#define M4U_LARB0_ID 0
+#define M4U_LARB1_ID 1
+#define M4U_LARB2_ID 2
+#define M4U_LARB3_ID 3
+
+/* larb0 */
+#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
+#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB0_ID, 1)
+#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)
+#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3)
+#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4)
+#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
+#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB0_ID, 6)
+#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7)
+#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 8)
+#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9)
+#define M4U_PORT_APU_READ MTK_M4U_ID(M4U_LARB0_ID, 10)
+#define M4U_PORT_APU_WRITE MTK_M4U_ID(M4U_LARB0_ID, 11)
+
+/* larb1 */
+#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB1_ID, 0)
+#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 1)
+#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 2)
+#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB1_ID, 3)
+#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 4)
+#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB1_ID, 5)
+#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB1_ID, 6)
+#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB1_ID, 7)
+#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB1_ID, 8)
+#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB1_ID, 9)
+#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 10)
+#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB1_ID, 11)
+#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 12)
+#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB1_ID, 13)
+#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB1_ID, 14)
+#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 15)
+#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 16)
+#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 17)
+#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 18)
+
+/* larb2 */
+#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0)
+#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1)
+#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB2_ID, 2)
+#define M4U_PORT_CAM_LCS MTK_M4U_ID(M4U_LARB2_ID, 3)
+#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4)
+#define M4U_PORT_CAM_CAM_SV0 MTK_M4U_ID(M4U_LARB2_ID, 5)
+#define M4U_PORT_CAM_CAM_SV1 MTK_M4U_ID(M4U_LARB2_ID, 6)
+#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB2_ID, 7)
+#define M4U_PORT_CAM_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 8)
+#define M4U_PORT_CAM_AFO MTK_M4U_ID(M4U_LARB2_ID, 9)
+#define M4U_PORT_CAM_SPARE MTK_M4U_ID(M4U_LARB2_ID, 10)
+#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB2_ID, 11)
+#define M4U_PORT_CAM_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 12)
+#define M4U_PORT_CAM_UFDI MTK_M4U_ID(M4U_LARB2_ID, 13)
+#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB2_ID, 14)
+#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 15)
+#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 16)
+#define M4U_PORT_CAM_WPE0_I MTK_M4U_ID(M4U_LARB2_ID, 17)
+#define M4U_PORT_CAM_WPE1_I MTK_M4U_ID(M4U_LARB2_ID, 18)
+#define M4U_PORT_CAM_WPE_O MTK_M4U_ID(M4U_LARB2_ID, 19)
+#define M4U_PORT_CAM_FD0_I MTK_M4U_ID(M4U_LARB2_ID, 20)
+#define M4U_PORT_CAM_FD1_I MTK_M4U_ID(M4U_LARB2_ID, 21)
+#define M4U_PORT_CAM_FD0_O MTK_M4U_ID(M4U_LARB2_ID, 22)
+#define M4U_PORT_CAM_FD1_O MTK_M4U_ID(M4U_LARB2_ID, 23)
+
+/* larb3 */
+#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB3_ID, 0)
+#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB3_ID, 1)
+#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB3_ID, 2)
+#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB3_ID, 3)
+#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB3_ID, 4)
+#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB3_ID, 5)
+#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB3_ID, 6)
+#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB3_ID, 7)
+#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB3_ID, 8)
+#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB3_ID, 9)
+#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB3_ID, 10)
+
+#endif
--
b4 0.10.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v6 2/3] iommu/mediatek: add support for 6-bit encoded port IDs
2022-11-02 15:18 [PATCH v6 0/3] iommu/mediatek: Add mt8365 iommu support Alexandre Mergnat
2022-11-02 15:18 ` [PATCH v6 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC Alexandre Mergnat
@ 2022-11-02 15:18 ` Alexandre Mergnat
2022-11-02 15:18 ` [PATCH v6 3/3] iommu/mediatek: add support for MT8365 SoC Alexandre Mergnat
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Alexandre Mergnat @ 2022-11-02 15:18 UTC (permalink / raw)
To: Matthias Brugger, Krzysztof Kozlowski, Joerg Roedel, Rob Herring,
Robin Murphy, Will Deacon, Yong Wu
Cc: linux-kernel, Alexandre Mergnat, iommu, linux-mediatek,
Amjad Ouled-Ameur, Markus Schneider-Pargmann, linux-arm-kernel,
Fabien Parent, AngeloGioacchino Del Regno, devicetree,
Krzysztof Kozlowski
From: Fabien Parent <fparent@baylibre.com>
Until now the port ID was always encoded as a 5-bit data. On MT8365,
the port ID is encoded as a 6-bit data. This requires to add extra
macro F_MMU_INT_ID_LARB_ID_EXT, and F_MMU_INT_ID_PORT_ID_EXT in order
to support 6-bit encoded port IDs.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
---
drivers/iommu/mtk_iommu.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 5a4e00e4bbbc..563e3c54a0e2 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -108,8 +108,12 @@
#define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3)
#define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7)
#define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7)
+/* Macro for 5 bits length port ID field (default) */
#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
+/* Macro for 6 bits length port ID field */
+#define F_MMU_INT_ID_LARB_ID_WID_6(a) (((a) >> 8) & 0x7)
+#define F_MMU_INT_ID_PORT_ID_WID_6(a) (((a) >> 2) & 0x3f)
#define MTK_PROTECT_PA_ALIGN 256
#define MTK_IOMMU_BANK_SZ 0x1000
@@ -139,6 +143,7 @@
#define IFA_IOMMU_PCIE_SUPPORT BIT(16)
#define PGTABLE_PA_35_EN BIT(17)
#define TF_PORT_TO_ADDR_MT8173 BIT(18)
+#define INT_ID_PORT_WIDTH_6 BIT(19)
#define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \
((((pdata)->flags) & (mask)) == (_x))
@@ -441,14 +446,19 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
fault_pa |= (u64)pa34_32 << 32;
if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) {
- fault_port = F_MMU_INT_ID_PORT_ID(regval);
if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) {
fault_larb = F_MMU_INT_ID_COMM_ID(regval);
sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
+ fault_port = F_MMU_INT_ID_PORT_ID(regval);
} else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) {
fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval);
sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval);
+ fault_port = F_MMU_INT_ID_PORT_ID(regval);
+ } else if (MTK_IOMMU_HAS_FLAG(plat_data, INT_ID_PORT_WIDTH_6)) {
+ fault_port = F_MMU_INT_ID_PORT_ID_WID_6(regval);
+ fault_larb = F_MMU_INT_ID_LARB_ID_WID_6(regval);
} else {
+ fault_port = F_MMU_INT_ID_PORT_ID(regval);
fault_larb = F_MMU_INT_ID_LARB_ID(regval);
}
fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
--
b4 0.10.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v6 3/3] iommu/mediatek: add support for MT8365 SoC
2022-11-02 15:18 [PATCH v6 0/3] iommu/mediatek: Add mt8365 iommu support Alexandre Mergnat
2022-11-02 15:18 ` [PATCH v6 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC Alexandre Mergnat
2022-11-02 15:18 ` [PATCH v6 2/3] iommu/mediatek: add support for 6-bit encoded port IDs Alexandre Mergnat
@ 2022-11-02 15:18 ` Alexandre Mergnat
2022-11-10 11:34 ` [PATCH v6 0/3] iommu/mediatek: Add mt8365 iommu support Matthias Brugger
2022-11-19 9:11 ` Joerg Roedel
4 siblings, 0 replies; 6+ messages in thread
From: Alexandre Mergnat @ 2022-11-02 15:18 UTC (permalink / raw)
To: Matthias Brugger, Krzysztof Kozlowski, Joerg Roedel, Rob Herring,
Robin Murphy, Will Deacon, Yong Wu
Cc: linux-kernel, Alexandre Mergnat, iommu, linux-mediatek,
Amjad Ouled-Ameur, Markus Schneider-Pargmann, linux-arm-kernel,
Fabien Parent, AngeloGioacchino Del Regno, devicetree,
Krzysztof Kozlowski
From: Fabien Parent <fparent@baylibre.com>
Add IOMMU support for MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Tested-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
---
drivers/iommu/mtk_iommu.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 563e3c54a0e2..aff7a9190749 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -170,6 +170,7 @@ enum mtk_iommu_plat {
M4U_MT8186,
M4U_MT8192,
M4U_MT8195,
+ M4U_MT8365,
};
struct mtk_iommu_iova_region {
@@ -1525,6 +1526,17 @@ static const struct mtk_iommu_plat_data mt8195_data_vpp = {
{4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}},
};
+static const struct mtk_iommu_plat_data mt8365_data = {
+ .m4u_plat = M4U_MT8365,
+ .flags = RESET_AXI | INT_ID_PORT_WIDTH_6,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
+ .banks_num = 1,
+ .banks_enable = {true},
+ .iova_region = single_domain,
+ .iova_region_nr = ARRAY_SIZE(single_domain),
+ .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
+};
+
static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
{ .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
@@ -1537,6 +1549,7 @@ static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra},
{ .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo},
{ .compatible = "mediatek,mt8195-iommu-vpp", .data = &mt8195_data_vpp},
+ { .compatible = "mediatek,mt8365-m4u", .data = &mt8365_data},
{}
};
--
b4 0.10.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v6 0/3] iommu/mediatek: Add mt8365 iommu support
2022-11-02 15:18 [PATCH v6 0/3] iommu/mediatek: Add mt8365 iommu support Alexandre Mergnat
` (2 preceding siblings ...)
2022-11-02 15:18 ` [PATCH v6 3/3] iommu/mediatek: add support for MT8365 SoC Alexandre Mergnat
@ 2022-11-10 11:34 ` Matthias Brugger
2022-11-19 9:11 ` Joerg Roedel
4 siblings, 0 replies; 6+ messages in thread
From: Matthias Brugger @ 2022-11-10 11:34 UTC (permalink / raw)
To: Alexandre Mergnat, Krzysztof Kozlowski, Joerg Roedel, Rob Herring,
Robin Murphy, Will Deacon, Yong Wu
Cc: linux-kernel, iommu, linux-mediatek, Amjad Ouled-Ameur,
Markus Schneider-Pargmann, linux-arm-kernel, Fabien Parent,
AngeloGioacchino Del Regno, devicetree, Krzysztof Kozlowski
On 02/11/2022 16:18, Alexandre Mergnat wrote:
> Hi,
>
> This series contains patches related to the support of mt8365 iommu.
> Thanks for your feedback so far.
>
> Regards,
> Alex
>
> Changes in v6:
> - Rebase
> - Add new trailers
> - Link to v5: https://lore.kernel.org/r/20221001-iommu-support-v5-0-92cdbb83bbb8@baylibre.com
>
> Changes in v5:
> - Fix name file in mediatek,iommu.yaml
> - Rename defines to be more consistent
> - Rework INT_ID_PORT_WIDTH_6 check
> - Link to v4: https://lore.kernel.org/r/20221001-iommu-support-v4-0-f1e13438dfd2@baylibre.com
>
> Changes in v4:
> - Typo
> - Rebase
> - Link to v3: https://lore.kernel.org/r/20221001-iommu-support-v3-0-c7b3059b0d16@baylibre.com
>
> Changes in v3:
> - Rename "mt8365-larb-port.h" to "mediatek,mt8365-larb-port.h"
> - Rework the macros which retrieve larb/port ID to improve human readability
> - Link to v2: https://lore.kernel.org/r/20221001-iommu-support-v2-0-dbfef2eeebc9@baylibre.com
>
> Changes in v2:
> - Rebase.
> - Change M4U_PORT_APU_READ & M4U_PORT_APU_WRITE port to avoid display
> conflict in larb0. These definitions are used for vpu0 device node.
> - Add dual license.
> - Retitle commit.
> - Rename to int_id_port_width for more detail.
> - Fix typo.
> - Set banks_enable and banks_num in mt8365_data to fix kernel panic at boot.
> - Link to v1 - https://lore.kernel.org/lkml/20220530180328.845692-1-fparent@baylibre.com/
>
> To: Yong Wu <yong.wu@mediatek.com>
> To: Joerg Roedel <joro@8bytes.org>
> To: Will Deacon <will@kernel.org>
> To: Robin Murphy <robin.murphy@arm.com>
> To: Rob Herring <robh+dt@kernel.org>
> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> To: Matthias Brugger <matthias.bgg@gmail.com>
> Cc: iommu@lists.linux.dev
> Cc: linux-mediatek@lists.infradead.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: Fabien Parent <fparent@baylibre.com>
> Cc: Markus Schneider-Pargmann <msp@baylibre.com>
> Cc: Amjad Ouled-Ameur <aouledameur@baylibre.com>
> Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
>
> ---
> Fabien Parent (3):
> dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC
> iommu/mediatek: add support for 6-bit encoded port IDs
> iommu/mediatek: add support for MT8365 SoC
>
> .../devicetree/bindings/iommu/mediatek,iommu.yaml | 2 +
> drivers/iommu/mtk_iommu.c | 25 +++++-
> .../dt-bindings/memory/mediatek,mt8365-larb-port.h | 90 ++++++++++++++++++++++
> 3 files changed, 116 insertions(+), 1 deletion(-)
> ---
> base-commit: 11082343e3bf2953a937509f0316cabf69dbf908
> change-id: 20221001-iommu-support-f409c7e094e6
>
For the whole series:
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v6 0/3] iommu/mediatek: Add mt8365 iommu support
2022-11-02 15:18 [PATCH v6 0/3] iommu/mediatek: Add mt8365 iommu support Alexandre Mergnat
` (3 preceding siblings ...)
2022-11-10 11:34 ` [PATCH v6 0/3] iommu/mediatek: Add mt8365 iommu support Matthias Brugger
@ 2022-11-19 9:11 ` Joerg Roedel
4 siblings, 0 replies; 6+ messages in thread
From: Joerg Roedel @ 2022-11-19 9:11 UTC (permalink / raw)
To: Alexandre Mergnat
Cc: Matthias Brugger, Krzysztof Kozlowski, Rob Herring, Robin Murphy,
Will Deacon, Yong Wu, linux-kernel, iommu, linux-mediatek,
Amjad Ouled-Ameur, Markus Schneider-Pargmann, linux-arm-kernel,
Fabien Parent, AngeloGioacchino Del Regno, devicetree,
Krzysztof Kozlowski
On Wed, Nov 02, 2022 at 04:18:06PM +0100, Alexandre Mergnat wrote:
> Fabien Parent (3):
> dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC
> iommu/mediatek: add support for 6-bit encoded port IDs
> iommu/mediatek: add support for MT8365 SoC
Applied, thanks.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-11-19 9:11 UTC | newest]
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2022-11-02 15:18 [PATCH v6 0/3] iommu/mediatek: Add mt8365 iommu support Alexandre Mergnat
2022-11-02 15:18 ` [PATCH v6 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC Alexandre Mergnat
2022-11-02 15:18 ` [PATCH v6 2/3] iommu/mediatek: add support for 6-bit encoded port IDs Alexandre Mergnat
2022-11-02 15:18 ` [PATCH v6 3/3] iommu/mediatek: add support for MT8365 SoC Alexandre Mergnat
2022-11-10 11:34 ` [PATCH v6 0/3] iommu/mediatek: Add mt8365 iommu support Matthias Brugger
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