From: Bjorn Helgaas <helgaas@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org,
kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
konrad.dybcio@somainline.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org,
dmitry.baryshkov@linaro.org,
Krishna Chaitanya Chundru <quic_krichai@quicinc.com>
Subject: Re: [PATCH v4 06/12] PCI: qcom-ep: Gate Master AXI clock to MHI bus during L1SS
Date: Wed, 5 Oct 2022 17:08:38 -0500 [thread overview]
Message-ID: <20221005220838.GA2400326@bhelgaas> (raw)
In-Reply-To: <20220914075350.7992-7-manivannan.sadhasivam@linaro.org>
[+cc Krishna]
On Wed, Sep 14, 2022 at 01:23:44PM +0530, Manivannan Sadhasivam wrote:
> During L1SS, gate the Master clock supplied to the MHI bus to save power.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> index 2dc6d4e44aff..526e98ea23f6 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> @@ -27,6 +27,7 @@
> #define PARF_SYS_CTRL 0x00
> #define PARF_DB_CTRL 0x10
> #define PARF_PM_CTRL 0x20
> +#define PARF_MHI_CLOCK_RESET_CTRL 0x174
> #define PARF_MHI_BASE_ADDR_LOWER 0x178
> #define PARF_MHI_BASE_ADDR_UPPER 0x17c
> #define PARF_DEBUG_INT_EN 0x190
> @@ -89,6 +90,9 @@
> #define PARF_PM_CTRL_READY_ENTR_L23 BIT(2)
> #define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5)
>
> +/* PARF_MHI_CLOCK_RESET_CTRL fields */
> +#define PARF_MSTR_AXI_CLK_EN BIT(1)
> +
> /* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */
> #define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0)
>
> @@ -394,6 +398,11 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
> pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);
> writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);
>
> + /* Gate Master AXI clock to MHI bus during L1SS */
> + val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
> + val &= ~PARF_MSTR_AXI_CLK_EN;
> + val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
Is this code executed when the link actually transitions to L1.x, or
is this just configuring things so that when the link does transition
to L1.x sometime later, hardware will gate the Master AXI clock?
Just curious because this looks more like *configuration*, i.e., the
latter, but there's the ongoing conversation about qcom system
suspend/resume, where IIUC, software is involved at least in some
L1.2 exits.
> dw_pcie_ep_init_notify(&pcie_ep->pci.ep);
>
> /* Enable LTSSM */
> --
> 2.25.1
>
next prev parent reply other threads:[~2022-10-05 22:08 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-14 7:53 [PATCH v4 00/12] Improvements to the Qcom PCIe Endpoint driver Manivannan Sadhasivam
2022-09-14 7:53 ` [PATCH v4 01/12] PCI: qcom-ep: Add kernel-doc for qcom_pcie_ep structure Manivannan Sadhasivam
2022-09-14 7:53 ` [PATCH v4 02/12] PCI: qcom-ep: Rely on the clocks supplied by devicetree Manivannan Sadhasivam
2022-09-14 7:53 ` [PATCH v4 03/12] PCI: qcom-ep: Make use of the cached dev pointer Manivannan Sadhasivam
2022-09-14 7:53 ` [PATCH v4 04/12] PCI: qcom-ep: Disable IRQs during driver remove Manivannan Sadhasivam
2022-09-14 7:53 ` [PATCH v4 05/12] PCI: qcom-ep: Expose link transition counts via debugfs Manivannan Sadhasivam
2022-09-14 7:53 ` [PATCH v4 06/12] PCI: qcom-ep: Gate Master AXI clock to MHI bus during L1SS Manivannan Sadhasivam
2022-10-05 22:08 ` Bjorn Helgaas [this message]
2022-10-05 22:24 ` Manivannan Sadhasivam
2022-09-14 7:53 ` [PATCH v4 07/12] PCI: qcom-ep: Disable Master AXI Clock when there is no PCIe traffic Manivannan Sadhasivam
2022-09-14 7:53 ` [PATCH v4 08/12] dt-bindings: PCI: qcom-ep: Make PERST separation optional Manivannan Sadhasivam
2022-09-14 7:53 ` [PATCH v4 09/12] " Manivannan Sadhasivam
2022-09-14 7:53 ` [PATCH v4 10/12] dt-bindings: PCI: qcom-ep: Define clocks per platform Manivannan Sadhasivam
2022-09-14 7:53 ` [PATCH v4 11/12] dt-bindings: PCI: qcom-ep: Add support for SM8450 SoC Manivannan Sadhasivam
2022-09-14 7:53 ` [PATCH v4 12/12] " Manivannan Sadhasivam
2022-10-03 7:00 ` [PATCH v4 00/12] Improvements to the Qcom PCIe Endpoint driver Manivannan Sadhasivam
2022-10-03 8:40 ` Lorenzo Pieralisi
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