From: Prabhakar <prabhakar.csengg@gmail.com>
To: Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Arnd Bergmann <arnd@arndb.de>, Olof Johansson <olof@lixom.net>,
soc@kernel.org, linux-arm-kernel@lists.infradead.org,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-riscv@lists.infradead.org
Cc: Conor Dooley <conor.dooley@microchip.com>,
Samuel Holland <samuel@sholland.org>,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Prabhakar <prabhakar.csengg@gmail.com>,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [RFC RESEND PATCH 0/2] RZ/G2UL separate out SoC specific parts
Date: Mon, 17 Oct 2022 10:11:59 +0100 [thread overview]
Message-ID: <20221017091201.199457-1-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to split up the RZ/G2UL SoC DTSI into common parts
so that this can be shared with the RZ/Five SoC.
Implementation is based on the discussion [0] where I have used option#2.
The Renesas RZ/G2UL (ARM64) and RZ/Five (RISC-V) have almost the same
identical blocks to avoid duplication a base SoC dtsi (r9a07g043.dtsi) is
created which will be used by the RZ/G2UL (r9a07g043u.dtsi) and RZ/Five
(r9a07g043F.dtsi)
Sending this as an RFC to get some feedback.
r9a07g043f.dtsi will look something like below:
#include <dt-bindings/interrupt-controller/irq.h>
#define SOC_PERIPHERAL_IRQ_NUMBER(nr) (nr + 32)
#define SOC_PERIPHERAL_IRQ(nr, na) SOC_PERIPHERAL_IRQ_NUMBER(nr) na
#include <arm64/renesas/r9a07g043.dtsi>
/ {
...
...
};
Although patch#2 can be merged into patch#1 just wanted to keep them separated
for easier review.
RFC-> RESEND RFC
* Patches rebased on [1]
RFC: [2]
[0] https://lore.kernel.org/linux-arm-kernel/Yyt8s5+pyoysVNeC@spud/T/
[1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221009230044.10961-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[2] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20220929172356.301342-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
Cheers,
Prabhakar
Lad Prabhakar (2):
arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro
to specify interrupt property
arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 347 ++++++++----------
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 72 ++++
.../boot/dts/renesas/r9a07g043u11-smarc.dts | 2 +-
3 files changed, 220 insertions(+), 201 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
--
2.25.1
next reply other threads:[~2022-10-17 9:12 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-17 9:11 Prabhakar [this message]
2022-10-17 9:12 ` [RFC RESEND PATCH 1/2] arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property Prabhakar
2022-10-25 12:28 ` Geert Uytterhoeven
2022-10-25 16:10 ` Lad, Prabhakar
2022-10-17 9:12 ` [RFC RESEND PATCH 2/2] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts Prabhakar
2022-10-25 12:37 ` Geert Uytterhoeven
2022-10-25 16:13 ` Lad, Prabhakar
2022-10-27 8:20 ` Lad, Prabhakar
2022-10-25 12:42 ` [RFC RESEND PATCH 0/2] RZ/G2UL separate out " Geert Uytterhoeven
2022-10-25 16:15 ` Lad, Prabhakar
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