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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id t11-20020a9d66cb000000b0063b24357269sm612592otm.13.2022.10.20.19.16.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 19:16:02 -0700 (PDT) Received: (nullmailer pid 2187016 invoked by uid 1000); Fri, 21 Oct 2022 02:16:04 -0000 Date: Thu, 20 Oct 2022 21:16:04 -0500 From: Rob Herring To: Akhil R Cc: ldewangan@nvidia.com, jonathanh@nvidia.com, vkoul@kernel.org, thierry.reding@gmail.com, p.zabel@pengutronix.de, dmaengine@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, sfr@canb.auug.org.au Subject: Re: [PATCH RESEND v2 3/3] dmaengine: tegra: Add support for dma-channel-mask Message-ID: <20221021021604.GA2181729-robh@kernel.org> References: <20221020083322.36431-1-akhilrajeev@nvidia.com> <20221020083322.36431-4-akhilrajeev@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221020083322.36431-4-akhilrajeev@nvidia.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, Oct 20, 2022 at 02:03:22PM +0530, Akhil R wrote: > Add support for dma-channel-mask so that only the specified channels > are used. This helps to reserve some channels for the firmware. > > This was initially achieved by limiting the channel number to 31 in > the driver and adjusting the register address to skip channel0 which > was reserved for a firmware. Now, with this change, the driver can > align more to the actual hardware which has 32 channels. > > Signed-off-by: Akhil R > Reviewed-by: Jon Hunter > --- > drivers/dma/tegra186-gpc-dma.c | 37 +++++++++++++++++++++++++++------- > 1 file changed, 30 insertions(+), 7 deletions(-) > > diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c > index fa9bda4a2bc6..1d1180db6d4e 100644 > --- a/drivers/dma/tegra186-gpc-dma.c > +++ b/drivers/dma/tegra186-gpc-dma.c > @@ -161,7 +161,10 @@ > #define TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT 5000 /* 5 msec */ > > /* Channel base address offset from GPCDMA base address */ > -#define TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET 0x20000 > +#define TEGRA_GPCDMA_CHANNEL_BASE_ADDR_OFFSET 0x10000 > + > +/* Default channel mask reserving channel0 */ > +#define TEGRA_GPCDMA_DEFAULT_CHANNEL_MASK 0xfffffffe > > struct tegra_dma; > struct tegra_dma_channel; > @@ -246,6 +249,7 @@ struct tegra_dma { > const struct tegra_dma_chip_data *chip_data; > unsigned long sid_m2d_reserved; > unsigned long sid_d2m_reserved; > + u32 chan_mask; > void __iomem *base_addr; > struct device *dev; > struct dma_device dma_dev; > @@ -1288,7 +1292,7 @@ static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec, > } > > static const struct tegra_dma_chip_data tegra186_dma_chip_data = { > - .nr_channels = 31, > + .nr_channels = 32, This is an ABI break. A new kernel with an old DTB will use 32 channels instead of 31. You should leave this and use the dma-channel-mask to enable all 32 channels. Rob