From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA4F8C38A2D for ; Mon, 24 Oct 2022 18:44:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230346AbiJXSoU (ORCPT ); Mon, 24 Oct 2022 14:44:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232165AbiJXSnn (ORCPT ); Mon, 24 Oct 2022 14:43:43 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E036F147074; Mon, 24 Oct 2022 10:25:51 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 401551477; Mon, 24 Oct 2022 07:17:12 -0700 (PDT) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 243153F792; Mon, 24 Oct 2022 07:17:04 -0700 (PDT) Date: Mon, 24 Oct 2022 15:17:01 +0100 From: Andre Przywara To: Icenowy Zheng Cc: Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Greg Kroah-Hartman , soc@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, Rob Herring Subject: Re: [PATCH v2 02/10] dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY Message-ID: <20221024151701.3dff5794@donnerap.cambridge.arm.com> In-Reply-To: <20221012055602.1544944-3-uwu@icenowy.me> References: <20221012055602.1544944-1-uwu@icenowy.me> <20221012055602.1544944-3-uwu@icenowy.me> Organization: ARM X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, 12 Oct 2022 13:55:54 +0800 Icenowy Zheng wrote: > Allwinner F1C100s has the most simple USB PHY among all Allwinner SoCs, > because it has only one OTG USB controller, no host-only OHCI/EHCI > controllers. > > Add a binding document for it. Following the current situation of one > YAML file per SoC, this one is based on > allwinner,sun8i-v3s-usb-phy.yaml, but with OHCI/EHCI-related bits > removed. (The same driver in Linux, phy-sun4i-usb, covers all these > binding files now.) > > Signed-off-by: Icenowy Zheng > Reviewed-by: Rob Herring > --- > Changes in v2: > - Clarify the relation with other phy-sun4i-usb bindings. > - Added Rob's ACK. > > .../phy/allwinner,suniv-f1c100s-usb-phy.yaml | 83 +++++++++++++++++++ > 1 file changed, 83 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml > new file mode 100644 > index 000000000000..22ff8e0f2331 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/allwinner,suniv-f1c100s-usb-phy.yaml > @@ -0,0 +1,83 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Allwinner F1C100s USB PHY Device Tree Bindings I see that commit dd3cb467ebb56 [1] discourages the redundant "Device Tree Bindings" suffix in the title name, so I think you should remove that. The rest looks alright to me, compared against the manual and what the driver expects, so with that fixed: Reviewed-by: Andre Przywara Cheers, Andre [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=dd3cb467ebb56 > + > +maintainers: > + - Chen-Yu Tsai > + - Maxime Ripard > + > +properties: > + "#phy-cells": > + const: 1 > + > + compatible: > + const: allwinner,suniv-f1c100s-usb-phy > + > + reg: > + maxItems: 1 > + description: PHY Control registers > + > + reg-names: > + const: phy_ctrl > + > + clocks: > + maxItems: 1 > + description: USB OTG PHY bus clock > + > + clock-names: > + const: usb0_phy > + > + resets: > + maxItems: 1 > + description: USB OTG reset > + > + reset-names: > + const: usb0_reset > + > + usb0_id_det-gpios: > + maxItems: 1 > + description: GPIO to the USB OTG ID pin > + > + usb0_vbus_det-gpios: > + maxItems: 1 > + description: GPIO to the USB OTG VBUS detect pin > + > + usb0_vbus_power-supply: > + description: Power supply to detect the USB OTG VBUS > + > + usb0_vbus-supply: > + description: Regulator controlling USB OTG VBUS > + > +required: > + - "#phy-cells" > + - compatible > + - clocks > + - clock-names > + - reg > + - reg-names > + - resets > + - reset-names > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + > + phy@1c13400 { > + compatible = "allwinner,suniv-f1c100s-usb-phy"; > + reg = <0x01c13400 0x10>; > + reg-names = "phy_ctrl"; > + clocks = <&ccu CLK_USB_PHY0>; > + clock-names = "usb0_phy"; > + resets = <&ccu RST_USB_PHY0>; > + reset-names = "usb0_reset"; > + #phy-cells = <1>; > + usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>; > + };