From: Dinh Nguyen <dinguyen@kernel.org>
To: jh80.chung@samsung.com
Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
sboyd@kernel.org, linux-mmc@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org
Subject: [PATCHv6 3/6] arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
Date: Wed, 26 Oct 2022 09:16:28 -0500 [thread overview]
Message-ID: <20221026141631.696863-3-dinguyen@kernel.org> (raw)
In-Reply-To: <20221026141631.696863-1-dinguyen@kernel.org>
The sdmmc controller's CIU(Card Interface Unit) clock's phase can be
adjusted through the register in the system manager. Add the binding
"altr,sysmgr-syscon" to the SDMMC node for the driver to access the
system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to
designate the smpsel and drvsel properties for the CIU clock.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v6: no changes
v5: new
---
arch/arm/boot/dts/socfpga.dtsi | 1 +
arch/arm/boot/dts/socfpga_arria10.dtsi | 1 +
arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi | 1 +
arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts | 1 +
arch/arm/boot/dts/socfpga_arria5.dtsi | 1 +
arch/arm/boot/dts/socfpga_cyclone5.dtsi | 1 +
arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi | 1 +
7 files changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 2459f3cd7dd9..604fc6e0c4ad 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -765,6 +765,7 @@ mmc: dwmmc0@ff704000 {
clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
clock-names = "biu", "ciu";
resets = <&rst SDMMC_RESET>;
+ altr,sysmgr-syscon = <&sysmgr 0x108 3>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 4370e3cbbb4b..b6ebe207e2bc 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -666,6 +666,7 @@ mmc: dwmmc0@ff808000 {
clocks = <&l4_mp_clk>, <&sdmmc_clk>;
clock-names = "biu", "ciu";
resets = <&rst SDMMC_RESET>;
+ altr,sysmgr-syscon = <&sysmgr 0x28 4>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
index ad7cd14de6b6..41f865c8c098 100644
--- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
@@ -73,6 +73,7 @@ &mmc {
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
+ clk-phase-sd-hs = <0>, <135>;
};
&osc1 {
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
index 64dc0799f3d7..d3969367f4b5 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -12,6 +12,7 @@ &mmc {
cap-mmc-highspeed;
broken-cd;
bus-width = <4>;
+ clk-phase-sd-hs = <0>, <135>;
};
&eccmgr {
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 22dbf07afcff..b531639ce7dc 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -23,6 +23,7 @@ mmc0: dwmmc0@ff704000 {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ clk-phase-sd-hs = <0>, <135>;
};
sysmgr@ffd08000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index 319a71e41ea4..a9d1ba66f1ff 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -23,6 +23,7 @@ mmc0: dwmmc0@ff704000 {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ clk-phase-sd-hs = <0>, <135>;
};
sysmgr@ffd08000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi
index bd92806ffc12..3b9daddf91cd 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi
@@ -18,5 +18,6 @@ memory@0 {
&mmc0 { /* On-SoM eMMC */
bus-width = <8>;
+ clk-phase-sd-hs = <0>, <135>;
status = "okay";
};
--
2.25.1
next prev parent reply other threads:[~2022-10-26 14:16 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-26 14:16 [PATCHv6 1/6] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Dinh Nguyen
2022-10-26 14:16 ` [PATCHv6 2/6] arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node Dinh Nguyen
2022-10-26 14:16 ` Dinh Nguyen [this message]
2022-10-26 14:16 ` [PATCHv6 4/6] mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase Dinh Nguyen
2022-11-02 15:41 ` Ulf Hansson
2022-10-26 14:16 ` [PATCHv6 5/6] clk: socfpga: remove the setting of clk-phase for sdmmc_clk Dinh Nguyen
2022-10-27 21:39 ` Stephen Boyd
2022-11-01 15:34 ` Dinh Nguyen
2022-10-26 14:16 ` [PATCHv6 6/6] arm: dts: socfpga: remove "clk-phase" in sdmmc_clk Dinh Nguyen
2022-10-26 20:50 ` [PATCHv6 1/6] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Rob Herring
2022-10-31 15:10 ` Dinh Nguyen
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