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From: Rob Herring <robh@kernel.org>
To: Dinh Nguyen <dinguyen@kernel.org>
Cc: jh80.chung@samsung.com, ulf.hansson@linaro.org,
	krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
	sboyd@kernel.org, linux-mmc@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-clk@vger.kernel.org
Subject: Re: [PATCHv6 1/6] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon"
Date: Wed, 26 Oct 2022 15:50:22 -0500	[thread overview]
Message-ID: <20221026205022.GA1291041-robh@kernel.org> (raw)
In-Reply-To: <20221026141631.696863-1-dinguyen@kernel.org>

On Wed, Oct 26, 2022 at 09:16:26AM -0500, Dinh Nguyen wrote:
> Document the optional "altr,sysmgr-syscon" binding that is used to
> access the System Manager register that controls the SDMMC clock
> phase.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
> v6: make "altr,sysmgr-syscon" optional
> v5: document reg shift
> v4: add else statement
> v3: document that the "altr,sysmgr-syscon" binding is only applicable to
>     "altr,socfpga-dw-mshc"
> v2: document "altr,sysmgr-syscon" in the MMC section
> ---
>  .../bindings/mmc/synopsys-dw-mshc.yaml        | 23 ++++++++++++++++---
>  1 file changed, 20 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
> index ae6d6fca79e2..0e2024eb9018 100644
> --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
> +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
> @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
>  
>  title: Synopsys Designware Mobile Storage Host Controller Binding
>  
> -allOf:
> -  - $ref: "synopsys-dw-mshc-common.yaml#"
> -
>  maintainers:
>    - Ulf Hansson <ulf.hansson@linaro.org>
>  
> @@ -38,6 +35,26 @@ properties:
>        - const: biu
>        - const: ciu
>  
> +allOf:
> +  - $ref: synopsys-dw-mshc-common.yaml#
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: altr,socfpga-dw-mshc
> +    then:
> +      properties:
> +        altr,sysmgr-syscon:
> +          $ref: /schemas/types.yaml#/definitions/phandle-array
> +          items:
> +            - description: phandle to the sysmgr node
> +            - description: register offset that controls the SDMMC clock phase
> +            - description: register shift for the smplsel(drive in) setting

This goes in the top-level. Use if/then schema to add constraints, not 
define properties.

> +    else:

Then you'll need to negate the if:  if: { not: { properties: ... }}

> +      properties:
> +        altr,sysmgr-syscon: false
> +
>  required:
>    - compatible
>    - reg
> -- 
> 2.25.1
> 
> 

  parent reply	other threads:[~2022-10-26 20:50 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-26 14:16 [PATCHv6 1/6] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Dinh Nguyen
2022-10-26 14:16 ` [PATCHv6 2/6] arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node Dinh Nguyen
2022-10-26 14:16 ` [PATCHv6 3/6] arm: " Dinh Nguyen
2022-10-26 14:16 ` [PATCHv6 4/6] mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase Dinh Nguyen
2022-11-02 15:41   ` Ulf Hansson
2022-10-26 14:16 ` [PATCHv6 5/6] clk: socfpga: remove the setting of clk-phase for sdmmc_clk Dinh Nguyen
2022-10-27 21:39   ` Stephen Boyd
2022-11-01 15:34     ` Dinh Nguyen
2022-10-26 14:16 ` [PATCHv6 6/6] arm: dts: socfpga: remove "clk-phase" in sdmmc_clk Dinh Nguyen
2022-10-26 20:50 ` Rob Herring [this message]
2022-10-31 15:10   ` [PATCHv6 1/6] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Dinh Nguyen

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