From: Stephen Boyd <sboyd@kernel.org>
To: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>,
Paul Cercueil <paul@crapouillou.net>
Cc: mturquette@baylibre.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, zhouyu@wanyeetech.com,
linux-mips@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/6] clk: ingenic: Make PLL clock "od" field optional
Date: Thu, 27 Oct 2022 14:51:02 -0700 [thread overview]
Message-ID: <20221027215104.E8CB4C433D6@smtp.kernel.org> (raw)
In-Reply-To: <sWPMeZZ7NP5UXWBsE8t41AGkBkpYIgpG@localhost>
Quoting Aidan MacDonald (2022-10-27 14:40:02)
>
> Paul Cercueil <paul@crapouillou.net> writes:
>
> > Hi Aidan,
> >
> > Le mer. 26 oct. 2022 à 20:43:40 +0100, Aidan MacDonald
> > <aidanmacdonald.0x0@gmail.com> a écrit :
> >> Add support for defining PLL clocks with od_bits = 0, meaning that
> >> OD is fixed to 1 and there is no OD field in the register. In this
> >> case od_max must also be 0, which is enforced with BUG_ON().
> >> Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
> >> ---
> >> v1 -> v2: Simplify od lookup in ingenic_pll_recalc_rate() and
> >> enforce od_max == 0 when od_bits is zero.
> >> drivers/clk/ingenic/cgu.c | 21 +++++++++++++++------
> >> drivers/clk/ingenic/cgu.h | 3 ++-
> >> 2 files changed, 17 insertions(+), 7 deletions(-)
> >> diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
> >> index 861c50d6cb24..3481129114b1 100644
> >> --- a/drivers/clk/ingenic/cgu.c
> >> +++ b/drivers/clk/ingenic/cgu.c
> >> @@ -83,7 +83,7 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long
> >> parent_rate)
> >> const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
> >> struct ingenic_cgu *cgu = ingenic_clk->cgu;
> >> const struct ingenic_cgu_pll_info *pll_info;
> >> - unsigned m, n, od_enc, od;
> >> + unsigned m, n, od, od_enc = 0;
> >> bool bypass;
> >> u32 ctl;
> >> @@ -96,8 +96,11 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long
> >> parent_rate)
> >> m += pll_info->m_offset;
> >> n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0);
> >> n += pll_info->n_offset;
> >> - od_enc = ctl >> pll_info->od_shift;
> >> - od_enc &= GENMASK(pll_info->od_bits - 1, 0);
> >> +
> >> + if (pll_info->od_bits > 0) {
> >> + od_enc = ctl >> pll_info->od_shift;
> >> + od_enc &= GENMASK(pll_info->od_bits - 1, 0);
> >> + }
> >> if (pll_info->bypass_bit >= 0) {
> >> ctl = readl(cgu->base + pll_info->bypass_reg);
> >> @@ -112,7 +115,11 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long
> >> parent_rate)
> >> if (pll_info->od_encoding[od] == od_enc)
> >> break;
> >> }
> >
> > I'd add a space there.
> >
> > With that:
> > Reviewed-by: Paul Cercueil <paul@crapouillou.net>
> >
>
> Already done; the space is there in my outbox and on lore.kernel.org.
> I think you might've accidentally removed it. Stephen's already
> applied the series anyway, so...
>
I fixed the whitespace.
next prev parent reply other threads:[~2022-10-27 21:51 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-26 19:43 [PATCH v2 0/6] Add support for X1000 audio clocks Aidan MacDonald
2022-10-26 19:43 ` [PATCH v2 1/6] clk: ingenic: Make PLL clock "od" field optional Aidan MacDonald
2022-10-27 12:38 ` Paul Cercueil
2022-10-27 21:40 ` Aidan MacDonald
2022-10-27 21:51 ` Stephen Boyd [this message]
2022-10-27 18:59 ` Stephen Boyd
2022-10-26 19:43 ` [PATCH v2 2/6] clk: ingenic: Make PLL clock enable_bit and stable_bit optional Aidan MacDonald
2022-10-27 12:39 ` Paul Cercueil
2022-10-27 18:59 ` Stephen Boyd
2022-10-26 19:43 ` [PATCH v2 3/6] clk: ingenic: Add .set_rate_hook() for PLL clocks Aidan MacDonald
2022-10-27 12:40 ` Paul Cercueil
2022-10-27 18:59 ` Stephen Boyd
2022-10-26 19:43 ` [PATCH v2 4/6] dt-bindings: ingenic,x1000-cgu: Add audio clocks Aidan MacDonald
2022-10-27 18:59 ` Stephen Boyd
2022-10-26 19:43 ` [PATCH v2 5/6] clk: ingenic: Add X1000 " Aidan MacDonald
2022-10-27 12:43 ` Paul Cercueil
2022-10-27 18:59 ` Stephen Boyd
2022-10-26 19:43 ` [PATCH v2 6/6] clk: ingenic: Minor cosmetic fixups for X1000 Aidan MacDonald
2022-10-27 12:44 ` Paul Cercueil
2022-10-27 19:00 ` Stephen Boyd
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