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[94.197.40.204]) by smtp.gmail.com with ESMTPSA id d13-20020adff84d000000b0023682011c1dsm3277496wrq.104.2022.10.28.03.34.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Oct 2022 03:34:28 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tsbogend@alpha.franken.de, perex@perex.cz, tiwai@suse.com Cc: alsa-devel@alsa-project.org, linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/3] ASoC: jz4740-i2s: Remove .set_sysclk() Date: Fri, 28 Oct 2022 11:34:18 +0100 Message-Id: <20221028103418.17578-4-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221028103418.17578-1-aidanmacdonald.0x0@gmail.com> References: <20221028103418.17578-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org .set_sysclk() is effectively unused here. No machine drivers use jz4740-i2s; and JZ4740_I2S_CLKSRC_EXT is the only selectable clock source with simple-card, but that is also the default source and has a fixed frequency, so configuring it would be redundant. simple-card ignores -ENOTSUPP error codes when setting the sysclock, so any device trees that do set the sysclock for some reason should still work. It's still possible to configure the clock parent manually in the device tree and control frequency using other simple-card options, so at the end of the day there's no real loss in functionality. Signed-off-by: Aidan MacDonald --- Meant to be applied on top of jz4740-i2s cleanups series already in linux-next. Link: https://lore.kernel.org/alsa-devel/20221023143328.160866-1-aidanmacdonald.0x0@gmail.com/ sound/soc/jz4740/jz4740-i2s.c | 32 -------------------------------- sound/soc/jz4740/jz4740-i2s.h | 10 ---------- 2 files changed, 42 deletions(-) delete mode 100644 sound/soc/jz4740/jz4740-i2s.h diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index b620d4462d90..6d9cfe0a5041 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -23,8 +23,6 @@ #include #include -#include "jz4740-i2s.h" - #define JZ_REG_AIC_CONF 0x00 #define JZ_REG_AIC_CTRL 0x04 #define JZ_REG_AIC_I2S_FMT 0x10 @@ -273,35 +271,6 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, return 0; } -static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, - unsigned int freq, int dir) -{ - struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - struct clk *parent; - int ret = 0; - - switch (clk_id) { - case JZ4740_I2S_CLKSRC_EXT: - parent = clk_get(NULL, "ext"); - if (IS_ERR(parent)) - return PTR_ERR(parent); - clk_set_parent(i2s->clk_i2s, parent); - break; - case JZ4740_I2S_CLKSRC_PLL: - parent = clk_get(NULL, "pll half"); - if (IS_ERR(parent)) - return PTR_ERR(parent); - clk_set_parent(i2s->clk_i2s, parent); - ret = clk_set_rate(i2s->clk_i2s, freq); - break; - default: - return -EINVAL; - } - clk_put(parent); - - return ret; -} - static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); @@ -318,7 +287,6 @@ static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = { .trigger = jz4740_i2s_trigger, .hw_params = jz4740_i2s_hw_params, .set_fmt = jz4740_i2s_set_fmt, - .set_sysclk = jz4740_i2s_set_sysclk, }; #define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \ diff --git a/sound/soc/jz4740/jz4740-i2s.h b/sound/soc/jz4740/jz4740-i2s.h deleted file mode 100644 index 4da14eac1145..000000000000 --- a/sound/soc/jz4740/jz4740-i2s.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _JZ4740_I2S_H -#define _JZ4740_I2S_H - -/* I2S clock source */ -#define JZ4740_I2S_CLKSRC_EXT 0 -#define JZ4740_I2S_CLKSRC_PLL 1 - -#endif -- 2.38.1