From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F293FA3741 for ; Fri, 28 Oct 2022 14:42:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229730AbiJ1Om4 (ORCPT ); Fri, 28 Oct 2022 10:42:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229996AbiJ1Omd (ORCPT ); Fri, 28 Oct 2022 10:42:33 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B66691F0410 for ; Fri, 28 Oct 2022 07:42:32 -0700 (PDT) Received: from ptx.hi.pengutronix.de ([2001:67c:670:100:1d::c0]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1ooQYy-0005tX-WB; Fri, 28 Oct 2022 16:42:25 +0200 Received: from mfe by ptx.hi.pengutronix.de with local (Exim 4.92) (envelope-from ) id 1ooQYy-0000X8-JX; Fri, 28 Oct 2022 16:42:24 +0200 Date: Fri, 28 Oct 2022 16:42:24 +0200 From: Marco Felsch To: "Peng Fan (OSS)" Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, Sherry Sun , devicetree@vger.kernel.org, Peng Fan , linux-kernel@vger.kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, festevam@gmail.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH V2 13/15] arm64: dts: imx8mm-evk: Enable usdhc1 to support wifi Message-ID: <20221028144224.dthligupldj2wift@pengutronix.de> References: <20221024031351.4135651-1-peng.fan@oss.nxp.com> <20221024031351.4135651-14-peng.fan@oss.nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221024031351.4135651-14-peng.fan@oss.nxp.com> User-Agent: NeoMutt/20180716 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::c0 X-SA-Exim-Mail-From: mfe@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: devicetree@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 22-10-24, Peng Fan (OSS) wrote: > From: Sherry Sun > > Enable usdhc1 which is used for wifi. > > Signed-off-by: Sherry Sun > Signed-off-by: Peng Fan > --- > arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 23 +++++++++++ > arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 39 +++++++++++++++++++ > 2 files changed, 62 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts > index a2b24d4d4e3e..c93387fcd498 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts > @@ -15,6 +15,17 @@ / { > aliases { > spi0 = &flexspi; > }; > + > + reg_sd1_vmmc: sd1_regulator { > + compatible = "regulator-fixed"; > + regulator-name = "WLAN_EN"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; > + off-on-delay = <20000>; This is wrong and also unnecessary for wifi? Regards, Marco > + startup-delay-us = <100>; > + enable-active-high; > + }; > }; > > &ddrc { > @@ -53,6 +64,18 @@ flash@0 { > }; > }; > > +&usdhc1 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; > + bus-width = <4>; > + vmmc-supply = <®_sd1_vmmc>; > + keep-power-in-suspend; > + non-removable; > + status = "okay"; > +}; > + > &usdhc3 { > assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; > assigned-clock-rates = <400000000>; > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > index 7d6317d95b13..ce450965e837 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > @@ -559,6 +559,45 @@ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 > >; > }; > > + pinctrl_usdhc1_gpio: usdhc1grpgpio { > + fsl,pins = < > + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 > + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 > + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 > + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 > + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 > + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 > + >; > + }; > + > + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { > + fsl,pins = < > + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 > + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 > + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 > + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 > + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 > + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 > + >; > + }; > + > + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { > + fsl,pins = < > + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 > + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 > + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 > + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 > + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 > + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 > + >; > + }; > + > pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { > fsl,pins = < > MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 > -- > 2.37.1 > > >