From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 038EFC38A02 for ; Fri, 28 Oct 2022 15:00:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230211AbiJ1PA3 (ORCPT ); Fri, 28 Oct 2022 11:00:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230199AbiJ1PA3 (ORCPT ); Fri, 28 Oct 2022 11:00:29 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6736F5754D for ; Fri, 28 Oct 2022 08:00:27 -0700 (PDT) Received: from ptx.hi.pengutronix.de ([2001:67c:670:100:1d::c0]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1ooQqM-0004cd-E0; Fri, 28 Oct 2022 17:00:22 +0200 Received: from mfe by ptx.hi.pengutronix.de with local (Exim 4.92) (envelope-from ) id 1ooQqM-0001OB-1B; Fri, 28 Oct 2022 17:00:22 +0200 Date: Fri, 28 Oct 2022 17:00:22 +0200 From: Marco Felsch To: "Peng Fan (OSS)" Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, devicetree@vger.kernel.org, Peng Fan , linux-kernel@vger.kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, festevam@gmail.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH V2 05/15] arm64: dts: imx8mp-evk: enable uart1/3 ports Message-ID: <20221028150021.dplhuorxr5w2bnux@pengutronix.de> References: <20221024031351.4135651-1-peng.fan@oss.nxp.com> <20221024031351.4135651-6-peng.fan@oss.nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221024031351.4135651-6-peng.fan@oss.nxp.com> User-Agent: NeoMutt/20180716 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::c0 X-SA-Exim-Mail-From: mfe@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: devicetree@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 22-10-24, Peng Fan (OSS) wrote: > From: Peng Fan > > Enable uart1/3 ports for evk board. > Configure the clock to source from IMX8MP_SYS_PLL1_80M, because the uart > could only support max 1.5M buadrate if using OSC_24M as clock source. > > Signed-off-by: Peng Fan LGTM, feel free to add my: Reviewed-by: Marco Felsch > --- > arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 36 ++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts > index 316390f917a4..b8a7de87ce4c 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts > @@ -428,6 +428,15 @@ &snvs_pwrkey { > status = "okay"; > }; > > +&uart1 { /* BT */ > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart1>; > + assigned-clocks = <&clk IMX8MP_CLK_UART1>; > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; > + fsl,uart-has-rtscts; > + status = "okay"; > +}; > + > &uart2 { > /* console */ > pinctrl-names = "default"; > @@ -450,6 +459,15 @@ &usb_dwc3_1 { > status = "okay"; > }; > > +&uart3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart3>; > + assigned-clocks = <&clk IMX8MP_CLK_UART3>; > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; > + fsl,uart-has-rtscts; > + status = "okay"; > +}; > + > &usdhc2 { > assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; > assigned-clock-rates = <400000000>; > @@ -625,6 +643,15 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 > >; > }; > > + pinctrl_uart1: uart1grp { > + fsl,pins = < > + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 > + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 > + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 > + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 > + >; > + }; > + > pinctrl_uart2: uart2grp { > fsl,pins = < > MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 > @@ -638,6 +665,15 @@ MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 > >; > }; > > + pinctrl_uart3: uart3grp { > + fsl,pins = < > + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 > + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 > + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 > + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 > + >; > + }; > + > pinctrl_usdhc2: usdhc2grp { > fsl,pins = < > MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 > -- > 2.37.1 > > >