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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id i16-20020a056870a69000b0013b8b3710bfsm3396902oam.13.2022.10.31.11.39.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 11:39:43 -0700 (PDT) Received: (nullmailer pid 3235802 invoked by uid 1000); Mon, 31 Oct 2022 18:39:45 -0000 Date: Mon, 31 Oct 2022 13:39:45 -0500 From: Rob Herring To: AngeloGioacchino Del Regno Cc: Tinghan Shen , Ryder Lee , Jianjun Wang , Bjorn Helgaas , Krzysztof Kozlowski , Matthias Brugger , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com Subject: Re: [PATCH v4 1/3] dt-bindings: PCI: mediatek-gen3: Support mt8195 Message-ID: <20221031183945.GA3060184-robh@kernel.org> References: <20221028094317.29270-1-tinghan.shen@mediatek.com> <20221028094317.29270-2-tinghan.shen@mediatek.com> <9da05c64-87bb-39c7-6c23-e4918bd5024b@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <9da05c64-87bb-39c7-6c23-e4918bd5024b@collabora.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Oct 31, 2022 at 02:28:54PM +0100, AngeloGioacchino Del Regno wrote: > Il 28/10/22 11:43, Tinghan Shen ha scritto: > > From: Jianjun Wang > > > > In order to support mt8195 pcie node, update the yaml to support new > > properties of iommu and power-domain, and update the reset-names > > property to allow only one 'mac' name. > > > > Signed-off-by: Jianjun Wang > > Signed-off-by: TingHan Shen > > --- > > .../bindings/pci/mediatek-pcie-gen3.yaml | 16 +++++++++++++--- > > 1 file changed, 13 insertions(+), 3 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > index c00be39af64e..a9013c10131a 100644 > > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > @@ -70,14 +70,21 @@ properties: > > minItems: 1 > > maxItems: 8 > > + iommu-map: > > + maxItems: 1 > > + > > + iommu-map-mask: > > + const: 0 > > + > > resets: > > minItems: 1 > > maxItems: 2 > > reset-names: > > - minItems: 1 > > - items: > > - - const: phy > > + oneOf: > > + - items: > > + - const: phy > > + - const: mac > > - const: mac > > Sorry, this looks a bit messy. > > I can propose two solutions, either: > > reset-names: > minItems: 1 > items: > - const: mac > - const: phy > ... and change the order in mt8192.dtsi; That doesn't work because originally 'phy' alone was allowed. You could do: minItems: 1 maxItems: 2 items: enum: [ phy, mac ] But for 2 items, either order would be allowed. Not great, but not a huge deal. > otherwise, something like > allOf: > - if: > properties: > compatible: > contains: > - const: mediatek,mt8195-pcie > ... invert reset-names > > I think that the first solution makes a bit more sense though, as the > PHY reset may be moved in a PCIE-PHY specific driver instead of being > managed here in pci-mediatek-gen3. That either makes sense or it doesn't. If it does, then you should go ahead and separate the phy rather than change the ABI twice. Rob