From: Manivannan Sadhasivam <mani@kernel.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
martin.petersen@oracle.com, jejb@linux.ibm.com,
andersson@kernel.org, vkoul@kernel.org,
krzysztof.kozlowski+dt@linaro.org, konrad.dybcio@somainline.org,
robh+dt@kernel.org, quic_cang@quicinc.com,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
linux-scsi@vger.kernel.org
Subject: Re: [PATCH 01/15] phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tables struct
Date: Tue, 1 Nov 2022 20:11:35 +0530 [thread overview]
Message-ID: <20221101144135.GC244012@thinkpad> (raw)
In-Reply-To: <748f41e1-cafc-e7eb-43ac-b8daacf88da4@linaro.org>
On Mon, Oct 31, 2022 at 09:50:59PM +0300, Dmitry Baryshkov wrote:
> On 31/10/2022 18:46, Manivannan Sadhasivam wrote:
> > On Sun, Oct 30, 2022 at 12:50:50AM +0300, Dmitry Baryshkov wrote:
> > > On 29/10/2022 17:16, Manivannan Sadhasivam wrote:
> > > > As done for Qcom PCIe PHY driver, let's move the register settings to the
> > > > common qmp_phy_cfg_tables struct. This helps in adding any additional PHY
> > > > settings needed for functionalities like HS-G4 in the future by adding one
> > > > more instance of the qmp_phy_cfg_tables.
> > > >
> > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > > ---
> > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 223 +++++++++++++-----------
> > > > 1 file changed, 126 insertions(+), 97 deletions(-)
> > > >
> > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
[...]
> > > > static int qmp_ufs_com_init(struct qmp_phy *qphy)
> > > > @@ -933,31 +977,16 @@ static int qmp_ufs_power_on(struct phy *phy)
> > > > struct qmp_phy *qphy = phy_get_drvdata(phy);
> > > > struct qcom_qmp *qmp = qphy->qmp;
> > > > const struct qmp_phy_cfg *cfg = qphy->cfg;
> > > > - void __iomem *tx = qphy->tx;
> > > > - void __iomem *rx = qphy->rx;
> > > > void __iomem *pcs = qphy->pcs;
> > > > void __iomem *status;
> > > > unsigned int mask, val, ready;
> > > > int ret;
> > > > - qmp_ufs_serdes_init(qphy);
> > > > -
> > > > - /* Tx, Rx, and PCS configurations */
> > > > - qmp_ufs_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1);
> > > > + qmp_ufs_serdes_init(qphy, &cfg->tables);
> > > > - if (cfg->lanes >= 2) {
> > > > - qmp_ufs_configure_lane(qphy->tx2, cfg->regs,
> > > > - cfg->tx_tbl, cfg->tx_tbl_num, 2);
> > > > - }
> > > > -
> > > > - qmp_ufs_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1);
> > > > -
> > > > - if (cfg->lanes >= 2) {
> > > > - qmp_ufs_configure_lane(qphy->rx2, cfg->regs,
> > > > - cfg->rx_tbl, cfg->rx_tbl_num, 2);
> > > > - }
> > > > + qmp_ufs_lanes_init(qphy, &cfg->tables);
> > > > - qmp_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
> > > > + qmp_ufs_pcs_init(qphy, &cfg->tables);
> > >
> > > I'd suggest going straight to qmp_ufs_init_registers, which would contain
> > > both serdes, lanes and pcs inits.
> > >
> >
> > That adds one more level of indirection which may not be needed here. Moreover,
> > I'm trying to be in sync with other qmp drivers, specifically the pcie one.
> > This helps in working with these drivers.
>
> Yes, I understand. However I hope that the respective patchset (including
> [1]) will be merged soon. Thus I suggest skipping the step and using the
> same function already.
>
> [1] https://lore.kernel.org/linux-phy/20221028133603.18470-10-johan+linaro@kernel.org/
>
Ah, I missed this series. Will use the common function then.
Thanks,
Mani
> >
> > Thanks,
> > Mani
> >
> > > > ret = reset_control_deassert(qmp->ufs_reset);
> > > > if (ret)
> > >
> > > --
> > > With best wishes
> > > Dmitry
> > >
> >
>
> --
> With best wishes
> Dmitry
>
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2022-11-01 14:41 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-29 14:16 [PATCH 00/15] ufs: qcom: Add HS-G4 support Manivannan Sadhasivam
2022-10-29 14:16 ` [PATCH 01/15] phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tables struct Manivannan Sadhasivam
2022-10-29 21:50 ` Dmitry Baryshkov
2022-10-31 15:46 ` Manivannan Sadhasivam
2022-10-31 18:50 ` Dmitry Baryshkov
2022-11-01 14:41 ` Manivannan Sadhasivam [this message]
2022-10-29 14:16 ` [PATCH 02/15] phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B mode Manivannan Sadhasivam
2022-10-29 21:51 ` Dmitry Baryshkov
2022-10-29 14:16 ` [PATCH 03/15] phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 mode Manivannan Sadhasivam
2022-10-29 21:54 ` Dmitry Baryshkov
2022-10-29 14:16 ` [PATCH 04/15] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC Manivannan Sadhasivam
2022-10-29 21:55 ` Dmitry Baryshkov
2022-10-29 14:16 ` [PATCH 05/15] phy: qcom-qmp-ufs: Move HS Rate B register setting to tables_hs_b Manivannan Sadhasivam
2022-10-29 21:55 ` Dmitry Baryshkov
2022-10-29 14:16 ` [PATCH 06/15] dt-bindings: ufs: Add "max-gear" property for UFS device Manivannan Sadhasivam
2022-10-31 21:35 ` Rob Herring
2022-10-29 14:16 ` [PATCH 07/15] arm64: dts: qcom: qrb5165-rb5: Add max-gear property to UFS node Manivannan Sadhasivam
2022-10-29 14:16 ` [PATCH 08/15] scsi: ufs: ufs-qcom: Remove un-necessary goto statements Manivannan Sadhasivam
2022-10-29 21:56 ` Dmitry Baryshkov
2022-10-29 14:16 ` [PATCH 09/15] scsi: ufs: ufs-qcom: Remove un-necessary WARN_ON() Manivannan Sadhasivam
2022-10-29 14:16 ` [PATCH 10/15] scsi: ufs: ufs-qcom: Use bitfields where appropriate Manivannan Sadhasivam
2022-10-29 21:58 ` Dmitry Baryshkov
2022-10-31 14:50 ` Manivannan Sadhasivam
2022-10-29 14:16 ` [PATCH 11/15] scsi: ufs: ufs-qcom: Use dev_err_probe() for printing probe error Manivannan Sadhasivam
2022-10-29 21:33 ` Dmitry Baryshkov
2022-10-29 14:16 ` [PATCH 12/15] scsi: ufs: ufs-qcom: Fix the Qcom register name for offset 0xD0 Manivannan Sadhasivam
2022-10-29 22:06 ` Dmitry Baryshkov
2022-10-31 14:50 ` Manivannan Sadhasivam
2022-10-29 14:16 ` [PATCH 13/15] scsi: ufs: ufs-qcom: Factor out the logic finding the HS Gear Manivannan Sadhasivam
2022-10-29 14:16 ` [PATCH 14/15] scsi: ufs: ufs-qcom: Add support for finding HS gear on new UFS versions Manivannan Sadhasivam
2022-10-29 21:48 ` Dmitry Baryshkov
2022-10-31 14:56 ` Manivannan Sadhasivam
2022-10-31 18:52 ` Dmitry Baryshkov
2022-11-02 20:05 ` Krzysztof Kozlowski
2022-11-03 12:18 ` Manivannan Sadhasivam
2022-10-31 15:39 ` Manivannan Sadhasivam
2022-10-29 14:16 ` [PATCH 15/15] MAINTAINERS: Add myself as the maintainer for Qcom UFS driver Manivannan Sadhasivam
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221101144135.GC244012@thinkpad \
--to=mani@kernel.org \
--cc=andersson@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=dmitry.baryshkov@linaro.org \
--cc=jejb@linux.ibm.com \
--cc=konrad.dybcio@somainline.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=linux-scsi@vger.kernel.org \
--cc=manivannan.sadhasivam@linaro.org \
--cc=martin.petersen@oracle.com \
--cc=quic_cang@quicinc.com \
--cc=robh+dt@kernel.org \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).