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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id em6-20020a0568705b8600b00127d2005ea1sm2079274oab.18.2022.11.04.11.03.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 11:03:37 -0700 (PDT) Received: (nullmailer pid 2087245 invoked by uid 1000); Fri, 04 Nov 2022 18:03:39 -0000 Date: Fri, 4 Nov 2022 13:03:39 -0500 From: Rob Herring To: Sibi Sankar Cc: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, sudeep.holla@arm.com, cristian.marussi@arm.com, agross@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, quic_avajid@quicinc.com Subject: Re: [RFC 1/2] dt-bindings: firmware: arm,scmi: Add support for memlat vendor protocol Message-ID: <20221104180339.GA2079655-robh@kernel.org> References: <1667451512-9655-1-git-send-email-quic_sibis@quicinc.com> <1667451512-9655-2-git-send-email-quic_sibis@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1667451512-9655-2-git-send-email-quic_sibis@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, Nov 03, 2022 at 10:28:31AM +0530, Sibi Sankar wrote: > Add bindings support for the SCMI QTI memlat (memory latency) vendor > protocol. The memlat vendor protocol enables the frequency scaling of > various buses (L3/LLCC/DDR) based on the memory latency governor > running on the CPUSS Control Processor. I thought the interconnect binding was what provided details for bus scaling. > > Signed-off-by: Sibi Sankar > --- > .../devicetree/bindings/firmware/arm,scmi.yaml | 164 +++++++++++++++++++++ > 1 file changed, 164 insertions(+) > > diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml > index 1c0388da6721..efc8a5a8bffe 100644 > --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml > +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml > @@ -189,6 +189,47 @@ properties: > reg: > const: 0x18 > > + protocol@80: > + type: object > + properties: > + reg: > + const: 0x80 > + > + qcom,bus-type: > + $ref: /schemas/types.yaml#/definitions/uint32-array > + items: > + minItems: 1 > + description: > + Identifier of the bus type to be scaled by the memlat protocol. > + > + cpu-map: cpu-map only goes under /cpus node. > + type: object > + description: > + The list of all cpu cluster configurations to be tracked by the memlat protocol > + > + patternProperties: > + '^cluster[0-9]': > + type: object > + description: > + Each cluster node describes the frequency domain associated with the > + CPUFREQ HW engine and bandwidth requirements of the buses to be scaled. > + > + properties: cpu-map nodes don't have properties. > + operating-points-v2: true > + > + qcom,freq-domain: Please don't add new users of this. Use the performance-domains binding instead. > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: > + Reference to the frequency domain of the CPUFREQ HW engine > + items: > + - items: > + - description: phandle to CPUFREQ HW engine > + - description: frequency domain associated with the cluster > + > + required: > + - qcom,freq-domain > + - operating-points-v2 > + > additionalProperties: false > > patternProperties: > @@ -429,4 +470,127 @@ examples: > }; > }; > > + - | > + #include > + > + firmware { > + scmi { > + compatible = "arm,scmi"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + mboxes = <&cpucp_mbox>; > + mbox-names = "tx"; > + shmem = <&cpu_scp_lpri>; > + > + scmi_memlat: protocol@80 { > + reg = <0x80>; > + qcom,bus-type = <0x2>; > + > + cpu-map { > + cluster0 { > + qcom,freq-domain = <&cpufreq_hw 0>; > + operating-points-v2 = <&cpu0_opp_table>; > + }; > + > + cluster1 { > + qcom,freq-domain = <&cpufreq_hw 1>; > + operating-points-v2 = <&cpu4_opp_table>; > + }; > + > + cluster2 { > + qcom,freq-domain = <&cpufreq_hw 2>; > + operating-points-v2 = <&cpu7_opp_table>; > + }; > + }; > + }; > + }; > + > + cpu0_opp_table: opp-table-cpu0 { > + compatible = "operating-points-v2"; > + > + cpu0_opp_300mhz: opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + opp-peak-kBps = <9600000>; > + }; > + > + cpu0_opp_1325mhz: opp-1324800000 { > + opp-hz = /bits/ 64 <1324800000>; > + opp-peak-kBps = <33792000>; > + }; > + > + cpu0_opp_2016mhz: opp-2016000000 { > + opp-hz = /bits/ 64 <2016000000>; > + opp-peak-kBps = <48537600>; > + }; > + }; > + > + cpu4_opp_table: opp-table-cpu4 { > + compatible = "operating-points-v2"; > + > + cpu4_opp_691mhz: opp-691200000 { > + opp-hz = /bits/ 64 <691200000>; > + opp-peak-kBps = <9600000>; > + }; > + > + cpu4_opp_941mhz: opp-940800000 { > + opp-hz = /bits/ 64 <940800000>; > + opp-peak-kBps = <17817600>; > + }; > + > + cpu4_opp_2611mhz: opp-2611200000 { > + opp-hz = /bits/ 64 <2611200000>; > + opp-peak-kBps = <48537600>; > + }; > + }; > + > + cpu7_opp_table: opp-table-cpu7 { > + compatible = "operating-points-v2"; > + > + cpu7_opp_806mhz: opp-806400000 { > + opp-hz = /bits/ 64 <806400000>; > + opp-peak-kBps = <9600000>; > + }; > + > + cpu7_opp_2381mhz: opp-2380800000 { > + opp-hz = /bits/ 64 <2380800000>; > + opp-peak-kBps = <44851200>; > + }; > + > + cpu7_opp_2515mhz: opp-2515200000 { > + opp-hz = /bits/ 64 <2515200000>; > + opp-peak-kBps = <48537600>; > + }; > + }; > + }; > + > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpucp_mbox: mailbox@17400000 { > + compatible = "qcom,cpucp-mbox"; > + reg = <0x0 0x17c00000 0x0 0x10>, <0x0 0x18590300 0x0 0x700>; > + interrupts = ; > + #mbox-cells = <0>; > + }; > + > + sram@18509400 { > + compatible = "mmio-sram"; > + reg = <0x0 0x18509400 0x0 0x400>; > + no-memory-wc; > + > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x0 0x18509400 0x400>; > + > + cpu_scp_lpri: scp-sram-section@0 { > + compatible = "arm,scmi-shmem"; > + reg = <0x0 0x80>; > + }; > + }; > + }; > + > ... > -- > 2.7.4 > >